Analog Devices,inc.

Christopher Daniel Dillon

Ahmed Mohamed Abdelatty Ali

Lawrence A Singer

Scott Gregory Bardsley

Paritosh Bhoraskar

Mitchell Hillis

Casey Hill

Peter Walther

Systems and methods for modifying the trigger assembly of a firearm to create different trigger pull weight stages during a pre-travel phase of the trigger, wherein the trigger pull weight of the pre-travel phase is greater than the trigger pull weight at the trigger breakpoint for the hammer to be released.

Firearm trigger assembly with multi-stage feature

Comparators are implemented in many circuits, including analog-to-digital converters (ADCs). Some ADCs demand high bandwidth, low power consumption, and high speed. To address these requirements, a comparator circuit can be implemented without a separate pre-amplifier, where a sampling network drives a latch directly. Specifically, the comparator circuit integrates a pre-amplifier within the latch in a manner that ensures low power and high speed operation.

Low power high bandwidth high speed comparator

A flip around amplifier circuit is provided that includes an amplifier having first and second amplification stages, a Miller capacitor, and a resistive element in series with the Miller capacitor, where an output line of the second amplification stage can be coupled to an output line of the first amplification stage through the Miller capacitor and the series resistive element. The circuit can include a feedback capacitor having a first plate coupled to an input line of the amplifier, and a flip around switch that can be operated so as to connect an output line of the amplifier to a second plate of the feedback capacitor. The circuit's classical transfer function can include a zero associated with the Miller capacitor and the series resistive element, and a pole associated with the feedback capacitor and the on-resistance of the flip around switch, where the zero is substantially equal to the pole.

Flip around switched capacitor amplifier

Signal sampler embodiments are provided for processing input signals along signal paths in response to mode-command signals. They include a follower transistor with a control terminal and a current terminal that establish at least part of a signal path. They also include a switched-capacitor network that receives signals from the current terminal in response to a first mode-command signal and that couple a selected one of a set of reference signals to the current terminal in response to a second mode-command signal. During a second mode-command signal, a bias switch is arranged to bias off the follower transistor by coupling a bias signal to the control terminal that approximates the selected reference signal. Accordingly, the amplitude of the reference signals can be increased to facilitate an increased dynamic range of the input signals without biasing the follower transistor into breakdown.

Signal samplers with enhanced dynamic range

A pipelined analog to digital converter. Each stage in the pipeline has a flash converter and a multiplying digital to analog converter. Each stage provides a digital bits and an analog residue that is passed to the next stage in the pipeline. The digital bits from all stages are combined in digital logic to produce the digital output of the converter. The flash converter in each stage has a set of comparators, each coupled to a reference ladder. A random number generator in connection with a switch matrix 'shuffles' the reference inputs to the comparators. The comparators are latched as soon as practical after they are stable and the reference inputs are shuffled as soon as practical after the comparators are latched. Also, a bandwidth trim circuit is provided to compensate for different cutoff frequencies of the input impedances of the flash and multiplying digital to analog converters.

Analog to digital converter with bandwidth tuning circuit

Data driver systems are provided that have programmable modes of operation to thereby facilitate selection of output signal forms and reduction of output ports in signal conditioning systems (e.g., analog-to-digital converters). The systems effectively reduce pin count by sharing pins between different drivers and selectively configuring the drivers in driver and high output-impedance states.

Data driver systems with programmable modes

Differential sampler structures are provided that reduce signal distortion and current demand. The structures include first and second buffers that drive first and second capacitors and first and second switches. First and second current pumps are capacitively coupled and also cross coupled to the first and second capacitors relative to the coupling of the first and second buffers to these capacitors. As a result, signal distortion and current demand are both reduced.

Differential sampler structures with reduced distortion and current demand

LVDS drivers and analog-to-digital (ADC) systems are provided which facilitate easy alteration (e.g., replacement of a selectable resistor R ) of differential current levels and differential voltages in response to altered loads. These drivers and systems maintain common-mode levels in the loads which are unaffected by alterations in the loads and their associated differential current and voltage levels.

Low voltage differential signaling (LVDS) drivers and systems

Latch structures and systems are disclosed that enhance latch speed and reduce latch current drain while providing complementary metal-oxide-semiconductor (CMOS)-level latch signals. They are realized with bipolar junction structures and CMOS structures that are arranged to limit latch currents in response to CMOS-level sense signals S .

Growing community of inventors

Greensboro, NC, United States of America

Christopher Daniel Dillon