Ncr Corporation

Lsi Logic Corporation

Christopher D Sonnek

Jon M Semerau

Kevin J Bruno

Steven J Musegades

Shailendra Kumar

Brian J Hinel

A single chip integrated remote access processor circuit has a plurality of communication interface units, including a local area network (LAN) interface unit, a first multi-protocol serial wide area network (SWAN) interface unit, a telephony coder-decoder interface unit and a peripheral component interface (PCI) unit. A data routing control circuit is coupled to the plurality of communication interface units for controlling data transfer between the interface units.

Single chip remote access processor

The multiplexing character processor of the present invention multiplexes data characters to and from a plurality of communication lines to a Central Processing Unit by bit slicing. Input data present on the plurality of communication lines is sampled at a rate which is at least 16 times the data bit rate and is formulated as a serial data bit stream. Each sample corresponds to a time slice which slice is allocated to a given communication line under the control of a scan list. A high data rate communication line can be placed on the scan list more than once to insure accurate data reproduction. Character assembly and disassembly is performed in an arithmetic logic unit (ALU) under program control, to provide the flexibility to support various communication link protocols. The input data on each communication line may have a different protocol. Synchronization of the serial data bits to the communication lines is performed by a data bit synchronizer DBS.

Multiplexing character processor

A test circuit for the output buffer of an integrated circuit permits testing for faults in the electrical connection of the output buffer to external conductors on a printed circuit board and for faults in the output buffer itself. A tester device supplies two test control signals to the test circuit for causing the output of the output buffer to be forced high, to be forced low, to pass the logic level of the internal data signal provided to the input of the output buffer, or to go into a tri-state (high impedance) condition.

Test circuit and method

A communications base microcontroller particularly adapted for use with a multiplexing character processor of the type that multiplexes data characters to and from a plurality of communication lines to a central processing unit. The communications base microcontroller is operable with communication lines carrying various protocols and data rates. A scan list and direction control stores the order in which the communication lines are to be scanned and the direction of the next data flow. An instruction execution unit in response to the scanning order set by the scan list fetches instruction words during a machine cycle preceding an execution cycle and provides operands and instructions each associated with the particular communication line being scanned. A program control device, in response to multiplexing rate (scan rate) established by the scan list stores the present instruction, the input protocol and other functions and selects a pointer to the next program instruction. The microcontroller thus permits the software associated with a particular protocol attached to a particular communication line to be run in a time sliced fashion in conjunction with the time slicing of data from the peripheral devices such that all peripheral devices are serviced without a contention process.

Communications base microcontroller

A data bit synchronizer particularly adapted for use with a multiplexing character processor of the type that multiplexes data characters to and from a plurality of communication lines to a central processing unit. The data bit synchronizer is operable with communication lines carrying various protocols and data bit rates. A RAM memory stores the control and status information for each of the plurality of communication lines. The RAM is accessed at a rate corresponding to the rate used to multiplex the communication lines to repeatedly output the information associated with each communication line. The data bit synchronizer also incorporates a bit rate clock generator for generating timing signals corresponding to selectable output data rates. A multiplexer is used to multiplex the timing signals with the control and status information.

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North St. Paul, MN, United States of America

Christopher D Sonnek