Rambus Inc.

Christopher D Holdenried

Marcus Van Ierssel

David J Cassan

Mehrdad Ramezani

Sang-Wook Paul Park

Ravi Shivnaraine

Hector Villacorta

Hui Song

Alain Rousson

The embodiments herein describe technologies for back-gate biasing of clock trees using a reference generator. A circuit includes a set of clock buffers and a programmable voltage reference generator to apply a voltage to a back gate of a transistor of the set of clock buffers.

Back-gate biasing of clock trees using a reference generator

A clock and data recovery circuit (CDR) includes a digitally controlled oscillator (DCO). A data sampler is coupled to receive a clock signal from the DCO. A deserializer includes an input coupled to an output of the data sampler. A first phase detector is coupled between a first output of the deserializer and a first input of the DCO. A second phase detector is coupled to a second output of the deserializer. An accumulator is coupled between an output of the second phase detector and a second input of the DCO. A frequency lock detection block is coupled to an output of the accumulator. An eye monitor is coupled to an input of the data sampler. The first phase detector controls a delay of the DCO and the accumulator controls a frequency of the DCO. An edge mute signal is coupled to the deserializer.

Deserialized dual-loop clock radio and data recovery circuit

Growing community of inventors

Toronto, Canada

Christopher D Holdenried