Trw Limited

Christopher D Glaeser

Bantwal R Rau

Philip J Kuekes

An interconnect circuit for use in a computer system employing horizontal architecture and having multiple resources of which the use must be scheduled in an optimum manner. The interconnect circuit reduces scheduling to a mechanical task by providing multi-word storage capability at each of a plurality of cross-points connected in data flow paths between the computer resources. At each cross-point of the interconnect circuit, data may be written into a selected location and retrieved from a selected location. Writing may be accomplished by an insertion operation in which already stored data is shifted to vacate the location selected for writing. Likewise, reading can be accompanied by a purge operation in which already stored data are shifted into the location from which a data word is purged. In this manner each cross-point can function as a time delay in a data path, to facilitate scheduling of resource usage.

Interconnect circuit

A computer system employing horizontal architecture and having multiple resources of which the use must be scheduled in an optimum manner. Scheduling is reduced to a mechanical task by the use of an interconnect circuit having multi-word storage capability at each of a plurality of cross-points providing data flow paths between the computer resources. At each cross-point of the interconnect circuit, data may be written into a selected location and retrieved from a selected location. Writing may be accomplished by an insertion operation in which already stored data is shifted to vacate the location selected for writing. Likewise, reading can be accompanied by a purge operation in which already stored data is shifted into the location from which data is purged. In this manner, each cross-point can function as a time delay in a data path, to facilitate scheduling of resource usage.

Easily schedulable horizontal computer

A memory circuit in which data words are held in a continuous sequence of locations, a new data word being insertable at a selected address, and a stored data word being readable from a selected address. On data word insertion, the selected location is first vacated by shifting data already stored above or below the selected address by one location. For example, all the data in locations having addresses equal to or greater than the selected address are shifted. Data read from the circuit may be optionally purged from the device and remaining data words are then shifted to fill the location vacated by the purged data. By appropriate selection of the various modes of operation, the memory circuit may be made to operate as a first-in-first-out memory, a last-in-first-out memory, or as a conventional random access memory. The circuit is well suited for use in a computer of the horizontal type, in which the use of computing resources has to be optimally scheduled, and data flowing between the resources has to be subjected to scheduled time delays.

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Fremont, CA, United States of America

Christopher D Glaeser