Amdahl Corporation

Christopher D Finan

Joseph A Petolino

Jeffrey A Thomas

Kevin L Daberkow

Daniel Carl Sobottka

Gary A Woffinden

Mark Semmelmeyer

Michael DeMar Taylor

Theodore S Robinson

James P Millar

Ajay K Shah

Robert A Ertl

Shen H Wang

Nicholas Y Pang

Jeffrey T Isozaki

Mehrzad Kasrazadeh

A computer system architecture implementing multiple central processing units, each including a split instruction and operand cache, and that provides for the management of multiple copies (line pairs) of a memory line through the use of a line pair state is described. Systematic management of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture implements the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the instruction and operand cache buffers of a single central processor. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depending on whether the operand buffer destination is a memory line that is a member of a line pair.

Computer system architecture implementing split instruction and operand

In a data processing system including a pipelined instruction execution unit and a pipelined high speed cache, a storage queue consisting of a set of FIFO registers and associated support logic handles transfer of data from the pipeline instruction execution unit to the high speed cache. When a store request flow from the instruction execution pipeline is forwarded to the high speed cache, instead of placing the data directly into the high speed cache, the starting address, length of store and data to be stored are placed into one of the store queue registers. The instruction execution unit sees the store request as completed and continues processing even though data has not been physically placed in the high speed cache. The write to the high speed cache is finished in the background at a later time during an unused storage pipeline cycle in the high speed cache.

Monolithic semi-custom IC having standard LSI sections and coupling gate

In a pipeline data processing machine having a first unit for execution of instructions running according to a first pipeline and a second unit for storing data from a plurality of ports running according to a second pipeline, the first unit having a result register for holding results including data and address information of a flow of the first pipeline, the present invention provides an apparatus for transferring results in the result register to the second unit. A plurality of registers connected to the result register, each storing the result from at least one flow of the first pipeline and storing control information is provided. Further, a controller in communication with the second unit and the plurality of ports responsive to the control information and a flow of the second pipeline is included for selecting one of the plurality of ports in a first-in, first-out queue as a port to the second unit and for updating the control information.

Cache storage queue

A system for updating an ECC code over a line in a data store when only part of the line has been updated is described. The system receives the update and its address, decodes the address to generate a first signal identifying the part of the line to be updated and a second signal identifying an un-updated part of the section. The data of the update and the first signal are used to generate a first partial error code. Data from the un-updated part of the line is read as the update is written to the store. The data from the un-updated part of the section and the second signal are used to generate a second partial error code. Finally, the first and second partial error codes are combined to generate the updated error code.

Cache error code update

A data processing machine includes an instruction unit that decodes and organizes a flow of instructions for processing data. In response to certain instructions, the instruction unit generates requests for storage unit resources. In addition, results generated in the instruction unit in response to certain instructions are supplied for storage in the storage unit. The storage unit selects in response to priority logic from completing requests for storage unit resources, including a high speed cache storing data, and a plurality of storage ports for transferring data from the result register to the high speed cache. Each of the storage ports generates requests for access to the high speed cache to transfer the data stored in the respective store ports to the cache. Storage unit priority is determined in part by predicting the fullness of the storage ports.

Cache storage priority

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Santa Clara, CA, United States of America

Christopher D Finan