Altera Corporation

Apple Inc.

Ciena Corporation

Christopher D Finan

Charles Francis Dominguez

Michael Bekerman

Kalpana Bansal

Remi Clavel

Alexander Ukanwa

Philippe Molson

Mark J Farley

Jean-Didier Allegrucci

Jeffrey J Irwin

Cora Lynn Mau

Ziad M Abu-Lebdeh

Harry Nguyen

Kenny Au

A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.

Precise time management using local time base

An apparatus for time management of a peripheral device is disclosed. A peripheral interface circuit receives information from a host circuit over a peripheral bus, the host circuit maintaining a global timebase in accordance with a first clock signal within a first clock domain. The peripheral interface circuit maintains, based om a second clock signal within a second clock domain, a first local timebase correlated to the global timebase. A peripheral control circuit operates in a third clock domain and maintains a second local timebase based on the first. The peripheral interface circuit determines phase and frequency differences between the second and third clock signals in determining a correlation between the second and first local timebases. A peripheral logic circuit in the third clock domain performs, operations that utilize a timestamp from the second local timebase, which accounts for correlation with the first local timebase.

Precise time management for peripheral device using local time base

Interface circuitry is provided to control the flow of data transmitted over a high-speed serial link. The interface circuitry may receive data over a high-speed serial link and store the received data in a receive buffer. The receive buffer may be connected to an additional buffer in an application layer module. The application layer module may produce credits based on the processing capacity of the additional buffer and send those credits to the interface circuitry. The interface circuitry may then send these credits over the high speed link.

High-speed peripheral component interconnect (PCIe) input-output devices with receive buffer management circuitry

An integrated circuit with a high-speed debug access port includes interface circuitry and a dedicated debug port in the interface circuitry. The interface circuitry includes a function circuit block that is used to receive a data packet from external circuitry coupled to the integrated circuit. The dedicated debug port is coupled to the function circuit block and is used to transmit the received data packet to debug circuitry on the integrated circuit. The interface circuitry may include a peripheral component interconnect express (PCIe) interface circuit.

Integrated circuit with a high-speed debug access port

One embodiment relates to an integrated circuit with a modular direct memory access system. A read data mover receives data obtained from a source address, and a write data mover for sends the data to a destination address. A descriptor controller provides the source address to the read data mover and the destination address to the write data mover. Another embodiment relates to a method of providing direct memory access. Another embodiment relates to a system which provides direct memory access. Other embodiments and features are also disclosed.

Modular direct memory access system

Modules and methods are described for buffering packets to be switched in a system, such as a programmed device. The modules can be configured for different packet lengths, protocols, applications, and/or designs in a larger system. Techniques and mechanisms are further described for implementing a central memory and a linked-list addressing scheme. Accordingly, memory blocks of the central memory can be used for variable length packets and further reused at substantially the same time as they become available, thereby improving packet switching efficiency and/or flexibility.

Configurable central memory buffered packet switch module for use in a PLD

An optical fiber ring network includes a plurality of interconnected nodes, each pair of neighboring nodes being interconnected by a pair of optical links. Using coarse wavelength division multiplexing, data is transmitted in both directions over each link, using a first wavelength &#x3bb;1 to transmit data in a first direction over the link and a second wavelength &#x3bb;2 to transmit data in a second, opposite direction over the link. The two wavelengths &#x3bb;1 and &#x3bb;2 differ by at least 10 nm. Each of the data streams transmitted over the optical link has a bandwidth of at least 2.5 Gbps. Further, each data stream has at least two logical streams embedded therein. A link multiplexer at each node of the network includes one or more link cards for coupling the link multiplexer to client devices, and one or more multiplexer units for coupling the link multiplexer to the optical links. Each link card includes frame buffers capable of storing numerous Fiber Channel frames that are being transmitted to and from the client device(s) coupled to that link card. The link card also includes flow control logic for pre-filling the frame buffers with frames of data before the receiving client devices send flow control messages to request their transmission. The combined effect of the frame buffers and flow control logic is that the full bandwidth of the links can be utilized even when the network nodes are very far apart and the client devices have small input data buffers.

Optical fiber ring communication system

An optical fiber ring network includes a plurality of interconnected nodes, each pair of neighboring nodes being interconnected by a pair of optical links. Using coarse wavelength division multiplexing, data is transmitted in both directions over each link, using a first wavelength &lgr; to transmit data in a first direction over the link and a second wavelength &lgr; to transmit data in a second, opposite direction over the link. The two wavelengths &lgr; and &lgr; differ by at least 10 nm. Each of the data streams transmitted over the optical link has a bandwidth of at least 2.5 Gbps. Further, each data stream has at least two logical streams embedded therein. A link multiplexer at each node of the network includes one or more link cards for coupling the link multiplexer to client devices, and one or more multiplexer units for coupling the link multiplexer to the optical links. Each link card includes frame buffers capable of storing numerous Fibre Channel frames that are being transmitted to and from the client device(s) coupled to that link card. The link card also includes flow control logic for pre-filling the frame buffers with frames of data before the receiving client devices send flow control messages to request their transmission. The combined effect of the frame buffers and flow control logic is that the full bandwidth of the links can be utilized even when the network nodes are very far apart and the client devices have small input data buffers.

Growing community of inventors

Cupertino, CA, United States of America

Christopher D Finan