Teradyne, Inc.

Christopher Croft Jones

Philip Luke Campbell

Christopher J Bruno

Adnan Khalid

Michael Francis McGoldrick

Jianfa Pei

An example test system includes test sites comprising test sockets for testing devices under test (DUTs) and pickers for picking DUTs from the test sockets or placing the DUTs into the test sockets. Each picker may include a picker head for holding a DUT. The test system also includes a gantry on which the pickers are mounted. The gantry may be configured to move the pickers relative to the test sites to position the pickers for picking the DUTs from the test sockets or placing the DUTs into the test sockets. The test sockets are arranged in at least one array that is accessible to the pickers on the gantry.

Automated test system

An example test system includes test sites that include sockets for testing devices under test (DUTs), pickers for picking DUTs from the sockets or placing the DUTs in the sockets, and a gantry on which the pickers are mounted. The gantry is configured to move the pickers relative to the test sites to position the pickers for picking the DUTs from the sockets or placing the DUTs into the sockets. The test system also includes one or more LASER range finders mounted on the gantry for movement over the DUTs in the sockets and in conjunction with movement of the pickers. A LASER range finder among the one or more LASER rangefinders mounted on the gantry is configured to detect a distance to a DUT placed into a socket.

Vision system for an automated test system

A system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period including a plurality of local edge generators receiving the clock signals, each local generator including local programmable means to record an absolute time at which to generate a timing signal in the current or future period and the means to generate that timing signal at a synchronous even sub-division of the clock period resolution. A separate time value is maintained allowing generated timing signals to be delayed by more than one period. An output delay circuit generates the timing signal responsive to a future time value and a phase offset. The phase offset can be provided using a clock multiplier and serial parallel converter to simplify hardware realizations.

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North Reading, MA, United States of America

Christopher Croft Jones