International Business Machines Corporation

Christopher Collier West

Justin Potok Bandholz

Pravin S Patel

Kevin Michael Reinberg

Clifton Ehrich Kerr

Philip Louis Weinstein

Joseph Eric Maxwell

Zachary Benson Durham

Challis Llewellyn Purrington

James Edward Hughes

Kevin S D Vernon

Kevin S Vernon

Bhyrav M Mutnury

Moises Cases

David Thomas Windell

Nam Huu Pham

Erdem Matoglu

Henry Gaines McMillan

Robert M Piper

Timothy Schlude

Bradley D Herman

Thomas D Pahel

Christopher Landon Wood

Warren D Bailey

Thomas Dixon Pahel, Jr

Michael Leo Scollard

Ivan R Zapata

Brian A Baker

Jack P Wong

Richard P Southers

Troy S Voytko

Maya P Yarbrough

Gwendolyn R Tobin

Christopher C Moody

Terry L Sawyers

Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights.

Optimizing a physical data communications topology between a plurality of computing nodes

Methods and systems for implementing such methods for providing server fault notifications, diagnostic and system management information may include, but are not limited to: receiving a network fault status request input; illuminating one or more server node fault indicators for one or more degraded server nodes having one or more faults; receiving a server node fault status request input for a degraded server node having one or more faults; and displaying one or more diagnostic service notifications for one or more faults of the degraded server node. The displaying of the diagnostic service notifications may allow for the completion of various service operations associated with the service notifications once the information specific to a fault is presented.

Server network diagnostic system

Wake on local area network (LAN) functionality is provided in a multi-root environment. An I/O device, which is share by a plurality of physical hosts, receives the MAC address contained in the wake up packet, then prepares and sends an appropriate wake signal to the targeted host. In one embodiment, the shared I/O device sends an out-of-band wake up signal to each of the physical host computers, wherein the wake up signal is a serial bit stream encoded with the MAC address so that only the physical host having a MAC address matching the MAC address in the wake up signal will be turned on. In another embodiment, the shared I/O device sends a binary ON/OFF signal directly to the targeted physical host computer over a signal line associated with the MAC address.

Wake on local area network signalling in a multi-root I/O virtualization

Methods and systems for implementing such methods for providing server diagnostic and system management information may include, but are not limited to: receiving a network fault status request input; illuminating one or more server node fault indicators for one or more degraded server nodes having one or more faults; receiving a server node fault status request input for a degraded server node having one or more faults; and displaying one or more diagnostic service notifications for one or more faults of the degraded server node. Display of diagnostic service notifications may allow for completion of various service operations associated with service notifications once information specific to a fault is presented. Such service operations may include placing a system in standby mode, transferring workloads to other systems, initiating a firmware update, placing the system in a mode that allows for physical maintenance, or ordering parts associated with one or more faults.

Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.

Fall time accelerator circuit

Methods, apparatus, and products for detecting an increase in thermal resistance of a heat sink in a computer system, the heat sink dissipating heat for a component of the computer system, the computer system including a fan controlling airflow across the heat sink, the computer system also including a temperature monitoring device, including: measuring, by a monitoring module through use of the temperature monitoring device during operation of the computer system, thermal resistance of the heat sink; determining whether the measured thermal resistance of the heat sink is greater than a threshold thermal resistance, the threshold thermal resistance stored in a thermal profile in non-volatile memory, and if the measured thermal resistance of the heat sink is greater than the threshold thermal resistance, notifying a system administrator.

Detecting an increase in thermal resistance of a heat sink in a computer system

The present invention is directed to the detection of faulty CPU heat sink coupling during system power-up. A method in accordance with an embodiment of the present invention includes: monitoring a slope of a CPU temperature rise from initial system power-up; determining if the slope of the CPU temperature rise exceeds an expected value; and in the case that the slope of the CPU temperature rise exceeds the expected value, indicating an existence of a possible fault (PFA) related to a heat sink coupled to the CPU.

Detecting faulty CPU heat sink coupling during system power-up

A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units ('CPUs'); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.

Structure for a memory switching data processing system

A memory switching data processing system including one or more central processing units ('CPUs'); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.

Memory switching data processing system

A system and method are used for electronically detecting the accumulation of dust within a computer system using a capacitive dust sensor. The dust detection system may be implemented on a smaller computer, such as an individual PC, or in a more expansive system, such as a rack-based server system ('rack system') having multiple servers and other hardware devices. In one embodiment, each server in a rack system includes a capacitive sensor responsive to the accumulation of dust. The capacitive sensor may include one or more capacitive plates integral with a heatsink. As dust collects on the capacitive plates, the capacitance increases. When a capacitance setpoint is reached, indicating the dust has reached a critical level, an alert is generated. The alerts may be received by a management console for the attention of a system administrator. Each alert may contain the identity of the server generating the alert, so that the system administrator knows which server(s) are to be removed for cleaning.

Capacitive detection of dust accumulation using microcontroller component leads

Printed circuit boards for countering signal distortion are disclosed that include: a conductive pathway on a printed circuit board between a transmitter and a receiver, the conductive pathway comprised of traces and vias connected together for conductive transfer of a signal from the transmitter to the receiver; a parasitic element on the printed circuit board, the parasitic element having a parasitic effect that distorts the signal; and one or more passive elements mounted adjacent to the conductive pathway without connecting to the conductive pathway, the passive elements having a corrective effect to reduce the distortion from the parasitic effect on the signal.

Printed circuit boards for countering signal distortion

A method of transmitting a signal on a bi-directional universal serial bus ('USB') circuit for boosting a signal on a USB bus disclosed. The circuit includes a first stage inverting buffer coupled to a second stage inverting buffer to form a non-inverting buffer circuit. A high pass filter is coupled in series with the non-inverting buffer circuit to provide AC coupling to the USB bus and to allow fast signal edges through the circuit. The booster circuit is arranged to improve signal quality over a USB bus to allow additional USB devices and longer USB busses to be utilized.

Bi-directional universal serial bus booster circuit

A simple, but intelligent watchdog circuit uses an up/down counter for its delay element. A watchdog event will occur if the counter is allowed to over flow or under flow its boundaries (in either direction). The system objective is to keep the counter within its boundaries by controlling the direction of the count. The count direction is simply a function of the Most Significant Bit (MSB) of the counter. Thus, the system must simply monitor the counters MSB and perform a little intelligent to determine the desired count direction.

Intelligent watchdog circuit

A bi-directional universal serial bus ('USB') circuit for boosting a signal on a USB bus disclosed. The circuit includes a first stage inverting buffer coupled to a second stage inverting buffer to form a non-inverting buffer circuit. A high pass filter is coupled in series with the non-inverting buffer circuit to provide AC coupling to the USB bus and to allow fast signal edges through the circuit. The booster circuit is arranged to improve signal quality over a USB bus to allow additional USB devices and longer USB busses to be utilized.

Growing community of inventors

Raleigh, NC, United States of America

Christopher Collier West