International Business Machines Corporation

Other

Globalfoundries Inc.

Kabushiki Kaisha Toshiba

Siemens Aktiengesellschaft

Infineon Technologies Ag

Infineon Technologies North America Corp.

Siemens Components, Inc.

Qimonda Ag

Christopher Carr Parks

Rajarao Jammy

Paul Christian Parries

Devendra K Sadana

Jack Allan Mandelman

Keith E Fogel

Keith Kwong Hon Wong

Joel Pereira De Souza

Andrew Herbert Simon

Steven John Koester

Edward William Kiewra

Shahab Siddiqui

Panayotis Constantinou Andricacos

Steven H Boettcher

Chih-Chao Yang

Cyprian Emeka Uzoh

Daniel C Edelstein

Oleg Gluschenkov

Takeshi Nogami

Cyril Cabral, Jr

Kenneth Parker Rodbell

Babar Ali Khan

Yun-Yu Wang

Johnathan E Faltermeier

David Edward Kotecki

Viraj Yashawant Sardesai

Ulrike Gruening

Ashima B Chakravarti

Johann Alsmeier

Patrick William Dehaven

Christine Dehm

James Anthony O'Neill

Paul Andrew Ronsheim

Donghun Kang

Nancy R Klymko

Stephen K Loh

Neal A Makela

Susan E Chaloux

Paul J Higgins

Roger Yen-Luen Tsai

John J Moore

Rohit S Takalkar

Jacob B Dadson

Louis L Hsu

Dechao Guo

Soon-Cheon Seo

Hariklia Deligianni

Michael Patrick Chudzik

Ravikumar Ramachandran

John Michael Cotte

Unoh Kwon

Thomas M Shaw

Tze-Chiang Chen

Balasubramanian S Haran

John David Baniecki

Michael P Belyansky

Anthony Gene Domenicucci

Nicolas Nagel

Klaus D Beyer

Xiaoyan Shao

Robert B Laibowitz

Erick G Walton

Tomio Katata

Kenneth T Settlemyer, Jr

Atul Champaklal Ajmera

Andreas Knorr

Wilma Jean Horkans

Peter Stevens Locke

Radhika Srinivasan

Keith Thomas Kwietniak

John I Kim

James Edward Fluegel

Eva Erika Simonyi

George G Gifford

Edward C Fredericks

Jean-Marc Rousseau

Stephen M Lucarini

Dean S Chung

Kathryn H Varian

Tsong-Lin Tai

John Preston Benedict

Zu-Jean Tien

David B Riggs

George L Mack

Thomas Wesley Joseph

Jerzy Kanicki

Shwu Jen Jeng

Tsong Lin Leo Tai

An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are contaminated with oxygen and fluorine particles. A lower blocking layer is formed within the opening, and the lower blocking layer contacts the bottom and walls of the opening. Also, a middle liner layer is formed within the opening, and the middle liner layer contacts the lower blocking layer. Additionally, an upper blocking layer is formed within the opening, and the upper blocking layer contacts the middle liner layer. Further, a conductor layer is formed within the opening, and the conductor layer contacts the upper blocking layer. The lower blocking layer prevents the fluorine particles from affecting the other layers.

Contact using multilayer liner

A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.

Copper interconnect structure and its formation

A method of forming a p-type semiconductor device is provided, which in one embodiment employs an aluminum containing threshold voltage shift layer to produce a threshold voltage shift towards the valence band of the p-type semiconductor device. The method of forming the p-type semiconductor device may include forming a gate structure on a substrate, in which the gate structure includes a gate dielectric layer in contact with the substrate, an aluminum containing threshold voltage shift layer present on the gate dielectric layer, and a metal containing layer in contact with at least one of the aluminum containing threshold voltage shift layer and the gate dielectric layer. P-type source and drain regions may be formed in the substrate adjacent to the portion of the substrate on which the gate structure is present. A p-type semiconductor device provided by the above-described method is also provided.

Scaling of metal gate with aluminum containing metal layer for threshold voltage shift

A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.

Technique to create a buried plate in embedded dynamic random access memory device

A method of preventing surface decomposition of a III-V compound semiconductor is provided. The method includes forming a silicon film having a thickness from 10 &#x212b; to 400 &#x212b; on a surface of an III-V compound semiconductor. After forming the silicon film onto the surface of the III-V compound semiconductor, a high performance semiconductor device including, for example, a MOSFET, can be formed on the capped/passivated III-V compound semiconductor. During the MOSFET fabrication, a high k dielectric can be formed on the capped/passivated III-V compound semiconductor and thereafter, activated source and drain regions can be formed into the III-V compound semiconductor.

Method to prevent surface decomposition of III-V compound semiconductors

The present disclosure relates to a microelectronic structure and the manufacture of the microelectronic structure. Specifically, the disclosure relates to an interconnect barrier layer between a rhodium contact structure and a copper interconnect structure in a microelectronic structure. The microelectronic structure provides for low resistance in microelectronic devices.

Method and structure of integrated rhodium contacts with copper interconnects

An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the surface oxidation problem of plating a conductive material onto a noble metal seed layer are provided. In accordance with the present invention, a hydrogen plasma treatment is used to treat a noble metal seed layer such that the treated noble metal seed layer is highly resistant to surface oxidation. The inventive oxidation-resistant noble metal seed layer has a low C content and/or a low nitrogen content.

Formation of oxidation-resistant seed layer for interconnect applications

Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &#x3bc;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.

Electroplated copper interconnection structure, process for making and electroplating bath

A trench isolation structure is formed in a substrate. One or more openings are formed in a surface of the substrate, and a liner layer is deposited at least along a bottom and sidewalls of the openings. A layer of doped oxide material is deposited at least in the openings, and the substrate is annealed to reflow the layer of doped oxide material. Only a portion near the surface of the substrate is removed from the layer of doped oxide material in the opening. A cap layer is deposited atop a remaining portion of the layer of doped oxide material in the opening.

Trench isolation employing a doped oxide trench fill

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Poughkeepsie, NY, United States of America

Christopher Carr Parks