Compaq Computer Corporation, Inc.

Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Christopher C Wanner

Kevin B Leigh

George D Megason

Paul R Culley

Robert A Lester

Dwight D Riley

Jeffrey C Stevens

David W Sherrod

David J Maguire

James R Edwards

Chandrakant D Patel

Keith Farkas

Alan L Goodrum

Gopalakrishnan Janakiraman

Randall L Hess

Dale J Mayer

David R Wooten

Bradley Dean Winick

John A Landry

Jeff W Wolford

Howard Leverenz

Robert L Woods

David E Murray

Michael Ruhovets

Guy E McSwain

Robert Stets

An example computing system may include computer module bays, a power subsystem to supply power to computer modules installed in the computer module bays, and a system controller. The power subsystem may also implement overcurrent protection (OCP) based on an OCP threshold parameter. The system controller may include dynamic OCP adjustment logic that repeatedly updates the OCP threshold parameter during normal operation of the computing system. The dynamic OCP adjustment logic may update the OCP threshold parameter by determining a power requirement of the computing system based on a current configuration of the computing system, determining a new OCP threshold based on the power requirement, and instructing the power subsystem to change a value of the OCP threshold parameter to a new value based on the new OCP threshold.

Dynamic OCP adjustment

Examples herein relate to an apparatus. In some examples, an apparatus may include a circuit to direct a power signal to at least one electrical component. The circuit may include a protection device to regulate power to the electrical component, detection circuitry to detect when the protection device has failed, and an alert handling logic to receive a signal from the detection circuitry that the protection device has failed.

Circuits to identify protection device failures

Examples disclose an electrical connector comprising a first pin and a second pin. Each pin has a different length corresponding to a different data signaling rate.

Multiple pins of different lengths corresponding to different data signaling rates

Various embodiments described herein provide for establishing connectivity of nodes by employing base management controllers associated with the nodes. For some embodiments, a first data is received at a resource manager from a first base management controller (BMC) associated with a first node, wherein the resource manager is associated with a server computer system. A second data is received at the resource manager from a second BMC associated with a second node. A classification of the first node and the second node are determined and a compatibility of the first node with the second node based on the first data and the second. A topology is generated, at the resource manager, of the first node and the second node.

Establishing connectivity of modular nodes in a pre-boot environment

A modular connector infrastructure includes device connector modules having optical connectors to optically connect to respective subsets of electronic devices in a system. The device connector modules are removably connected to the electronic devices.

Connector modules to optically connect to electronic devices

At least one computer system receives power from a power system having a maximum power output based on a nominal power consumption of the at least one computer system. The power system is operable to detect an amount of power consumed by the at least one computer system, and compare the power consumption to a threshold based on the maximum power output of the power supply. The power system is operable to place one or more components of the at least one computer system in a lower-power state to reduce power consumption in response to the amount of power consumed by the at least one computer system exceeding the threshold.

Controlling power consumption of at least one computer system

A memory subsystem includes multiple memory modules coupled by point-to-point links. A memory controller is coupled by a point-to-point link to a first memory module, which is turn is coupled by another point-to-point link to another memory module. Further memory modules may be coupled by respective point-to-point links in the memory subsystem. In some arrangements, each memory module tracks commands issued to other memory modules, such as more upstream memory modules. Also, in one example implementation, a clock is embedded within a data stream transmitted over a point-to-point link, so that an external clock is not employed in this example implementation.

Providing an arrangement of memory devices to enable high-speed data access

A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

Interfacing direct memory access devices to a non-ISA bus

A keyboard system according to the present invention includes a serial bus host controller coupled to a serial bus keyboard. The keyboard includes both keyboard scan logic and scan code conversion logic for passing to the host controller over the serial bus. The host controller includes circuitry for processing the data between the serial bus and a host bus. The host controller further includes 8042 emulation logic for providing a hardware compatible interface to the keyboard controller. The 8042 emulation logic also includes circuitry for communicating over the serial bus during times when the serial bus has not yet been initialized.

Universal serial bus keyboard system

A method or apparatus of blocking access to a first device via a bus carrying an address enable signal in a computer system. A second device detects appearance of predetermined bus address information, and the address enable signal is blocked from the first device if the predetermined bus address information is present. A third device connected to the bus and the first device both are responsive to the predetermined bus address information, which includes bus addresses having upper bits with a non-zero value.

Blocking address enable signal from a device on a bus

An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.

Arrangement of DMA, interrupt and timer functions to implement

A buffer and synchronization circuit for a computer system which provides synchronization of the column address strobe (CAS) signals provided to the memory DRAMs and which interlocks the memory data latch enable with the CAS signals provided from the memory controller without adding extra clock cycles or wait states. A synchronized buffer circuit receives the CAS signals from the memory controller and provides a plurality of synchronized duplicate CAS signals to the memory DRAMs. The synchronized buffer circuit includes several gate drivers in a single semiconductor chip so that each of the drivers has approximately the same delay in order to minimize skew between the duplicated CAS signals. An interlocking buffer circuit receives the memory data latch enable signal and the CAS signals from the memory controller and provides a synchronized memory latch enable to the data buffers. The buffer and synchronization circuit according to the present invention interlocks the memory latch enable to the CAS signals so that the latch enable is not negated prematurely regardless of the premature negation of the memory data latch enable from the memory controller.

Memory column address strobe buffer and synchronization and data latch

A computer system which includes a direct memory access (DMA) controller which can provide a 32 bit memory address and yet can also provide 24 bit memory address operation to remain compatible with previous systems. The DMA controller also monitors system operation and if only 24 bit address operations are occurring under the control of an external bus master or the DMA controller, the DMA controller drives the top memory address byte provided to a cache memory controller to help insure cache coherency. Additionally, the DMA controller can provide optimal time transfers for word width transfer between an odd starting memory address and an even starting input/output port.

Growing community of inventors

Tomball, TX, United States of America

Christopher C Wanner