Achronix Semiconductor Corporation

Christopher C LaFrieda

Virantha N Ekanayake

Raymond Nijssen

Rajit Manohar

Clinton W Kelly

Marcel Van Der Goot

Kamal Chaudhary

Ilya K Ganusov

Gael Paul

Sarma Jonnavithula

Mohan Krishna Vedam

Namit Varma

Hong Tam

Distribution of a reset signal across a system-on-chip (SoC) may be the highest latency signal in the circuit. As a result, the operating frequency of the device is reduced to ensure that the reset signal reaches all intellectual property (IP) blocks during a single clock cycle. A reset synchronizer receives the clock signal and the reset signal as inputs and generates a synchronous reset signal as an output. The synchronous reset signal has a fixed timing relationship with the clock signal. The clock signal may be paused when a reset signal is received. As a result, distribution of the synchronous reset signal may be performed without regard to the latency of the signal. After the synchronous reset signal has been received by all of the IP blocks, reset is deasserted and the clock signal is resumed.

Synchronous reset deassertion circuit

A four-input lookup table ('LUT4') is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.

Adder circuit using lookup tables

A conflict-free parallel radix sorting algorithm, and devices and systems implementing this algorithm, schedules memory copies of data elements of a large dataset so that there is always a single copy to each target memory each cycle of operation for the system implementing the algorithm. The conflict-free parallel radix sorting algorithm eliminates memory copying conflicts in copying data elements from different source memories to the same target memory and in this way maintains maximum throughput for the copying of data elements from source memories to target memories, reducing the time required to sort the data elements of the large dataset.

Conflict-free parallel radix sorting device, system and method

A four-input lookup table ('LUT4') is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table ('LUT6') is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.

Circuits comprising asynchronous linear pipelines and one-phase pipelines, and methods of forming asynchronous linear pipeline circuits and converting them to one-phase pipeline circuits are provided. Additional circuits, systems and methods are disclosed.

One phase logic

A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and one or more additional tokens into the converted asynchronous circuit. The circuit is initialized with a desired additional number of tokens placed in the asynchronous circuit, or a desired number of tokens are inserted at an input before taking tokens from an output.

Token enhanced asynchronous conversion of synchonous circuits

Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.

Asynchronous conversion circuitry apparatus, systems, and methods

A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input. One or more asynchronous outputs at a circuit boundary is converted to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output.

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Ridgefield, NJ, United States of America

Christopher C LaFrieda