National Semiconductor Corporation

Christopher C Joyce

Murray J Robinson

Tim Wah Luk

Timwah Luk

An improved Schottky transistor structure (6), including a bipolar transistor structure (7) and a Schottky diode structure (8), is formed by retrograde diffusing relatively fast diffusing atoms to form a localized retrograde diode well (9) as the substrate for the Schottky diode structure. An expanded buried collector layer (11) formed of relatively slow diffusing atoms underlies the base and collector regions of the bipolar transistor structure (7) and the retrograde diode well (9). A diode junction (10) is formed by expanding the base contact of the bipolar transistor structure to include the surface of the retrograde diode well. Preferably, the diode junction is a Platinum-Silicide junction. The improved Schottky transistor structure may be formed as part of a bipolar junction transistor fabrication process or a BICMOS integrated circuit fabrication process wherein the buried diode layer may be formed at the same time as the buried collector layer of the bipolar transistor structure and the retrograde diode well may be formed at the same time as the sub-emitter collector region of the bipolar transistor structure. The buried collector layer definition mask is also a buried diode layer definition mask, the sub-emitter collector region definition mask is also a retrograde diode well definition mask, and the bipolar contacts definition mask is also a diode junction contact definition mask.

Retrograde NWell cathode Schottky transistor and fabrication process

A lateral PNP transistor structure is fabricated in a BICMOS process utilizing the same steps as are used during the BICMOS process for fabricating NPN and CMOS transistors without requiring additional steps. A base N+ buried layer B/N+BL formed in the IC substrate P/SUB underlies the bipolar PNP transistor. A base Retro NWELL B/NWELL and a base contact Retro NWELL BC/NWELL are formed in the base N+ buried layer B/N+BL using the CMOS Retro NWELL mask, etch and N type introduction sequence. An epitaxial layer EPI of undoped or low doped EPI is deposited across the IC substrate and isolation oxide regions ISOX isolating the PNP transistor are grown during the isolation oxide ISOX mask, etch and grow sequence. The NPN collector sink definition mask, etch and N type introduction sequence is used to form a PNP base contact N+ sink region BC/N+SINK to the BC/NWELL and B/N+BL. A field oxide spacer FOX is grown during the CMOS active area definition mask, etch and grow sequence for separating the PNP BC/N+SINK from the PNP collector region P+C. A uniform layer of polysilicon POLY is masked and etched during the POLY definition mask and etch sequence to form a self aligned transistor SAT POLY mask for critically defining the PNP base width and base active region. The PNP collector region P+C and emitter region P+E are introduced through the SAT POLY mask using at least one of the NPN base definition mask, etch and P type introduction sequence and PMOS P+S/D mask definition, etch and P type introduction sequence. The PNP base contact region can be formed using the NPN emitter definition mask sequence. The PNP transistor contact surfaces and metal contacts are thereafter prepared according to conventional procedures.

Process for fabricating lateral PNP transistor structure and BICMOS IC

An improved Schottky diode structure (4) is formed by retrograde diffusing an N.sup.+ concentration of relatively fast diffusing atoms, preferably Phosphorus atoms, to form a localized diode NWell (6) as the diode substrate for the diode. A buried diode layer (5) formed of relatively slow diffusing N type atoms, preferably Antimony atoms, underlies the diode NWell and electrically couples the diode junction (7) to the diode ohmic contact (9). A diode ohmic contact region (31) underlies the ohmic contact, further coupling the diode junction to the ohmic contact. Preferably, the diode junction is a Platinum-Silicide junction. The improved Schottky diode structure may be formed as part of a BICMOS integrated circuit fabrication process wherein the buried diode layer may be formed at the same time as a buried collector layer of a bipolar transistor structure, the diode NWell may be formed at the same time as an NWell of a CMOS transistor structure and the diode ohmic contact region may be formed at the same time as a collector sink region. In the BICMOS fabrication process the buried collector layer definition mask is also a buried diode layer definition mask, the retro NWell definition mask is also a diode NWell definition mask, the collector sink definition mask is also a diode ohmic contact region definition mask, and the BICMOS contacts definition mask is also a diode junction and ohmic contact definition mask.

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Gorham, ME, United States of America

Christopher C Joyce