Intel Corporation

Digital Equipment Corporation

Christopher C Gianos

Joel James McCormack

Larry D Seiler

Bret L Toll

Ravishankar Iyer

Andrew J Herdrich

Ronak Singhal

Edwin Verplanke

Julius Yuli Mandelblat

Jeffrey D Chamberlain

Robert Stephen McNamara

James T Claffey

Subramaniam M Maiyuran

Norman Paul Jouppi

Maurice B Steinman

Tim Frodsham

Robert P Adler

Warren Anderson

Suresh Balasubramanian

Kenneth W Correll

Tracey L Gustafson

Horst W Wagner

Andrew V Hoar

Lichen Weng

Danny Paul Eggleston

Barton W Berkowitz

Richard M Watson

Systems, methods, and apparatuses for resource bandwidth monitoring and control are described. For example, in some embodiments, an apparatus comprising a requestor device to send a credit based request, a receiver device to receive and consume the credit based request, and a delay element in a return path between the requestor and receiver devices, the delay element to delay a credit based response from the receiver to the requestor are detailed.

Systems, apparatuses, and methods for resource bandwidth enforcement

In an embodiment, a system on chip includes: a plurality of local networks having one or more local endpoints and a first router, where at least some of the one or more local endpoints of different local networks have non-unique port identifiers; at least one global network having one or more global endpoints and at least one second router, where the one or more global endpoints have unique port identifiers; and a plurality of transparent bridges to couple between one of the plurality of local networks and the at least one global network. Other embodiments are described and claimed.

Method, apparatus and system for hierarchical network on chip routing

Systems and methods for cache allocation with code and data prioritization. An example system may comprise: a cache; a processing core, operatively coupled to the cache; and a cache control logic, responsive to receiving a cache fill request comprising an identifier of a request type and an identifier of a class of service, to identify a subset of the cache corresponding to a capacity bit mask associated with the request type and the class of service.

Cache allocation with code and data prioritization

Methods and apparatus to transfer data between one or more clock domains are described. In one embodiment, a plurality of signals corresponding to write pointers of a buffer and a read pointer of the buffer are generated. The signals corresponding to the write pointers of the buffer are to be generated based on different data patterns for transmission over different channels. Other embodiments are also claimed and described.

Multi-channel fractional clock data transfer

In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock domain of the first device, and providing the data to a functional unit of the first device at a deterministic time. In such manner, the two devices may operate in lockstep fashion. Other embodiments are described and claimed.

Deterministic operation of an input/output interface

The invention includes an apparatus and method for buffering data transmitted by a processor and received by an I/O device via a memory and buses. The memory arranged at a plurality of levels includes a lower level of the memory operating faster than a higher level of the memory. A plurality of ring buffers are allocated at different levels of the memory and available buffers at a lowest possible level of the memory are preferentially selected as write buffers to store data transmitted by the processor. The apparatus includes a first level of the memory arranged on an integrated circuit with the processor, a second level of the memory arranged in an off-chip cache, and a third level of the memory arranged in a dynamic random access memory. Read buffers are selected to store data to be received by the I/O device. Stored control values indicate the order for selecting the read buffers and are used by the processor to select the write buffer. Control values are stored in sets of registers located in the I/O device and in a software-based set of registers located in the dynamic random access memory. A selection register located in the I/O device indicates the selected read buffer.

Hierarchical ring buffers for buffering data between processor and I/O

A cache includes an address cache for storing memory addresses. An address queue is connected to the address cache for storing missed addresses in the order that the address cache is probed. A memory controller receives the missed addresses from the address queue. A data queue receives data stored at the missed addresses from the memory controller. A probe result queue is connected to the address cache for storing data cache line addresses and hit/miss information. A multiplexer connected to the data cache, the data queue, and the probe result queue selects output data from the data cache or the data queue depending on the hit/miss information.

Apparatus and method for providing non-blocking pipelined cache

A graphics system for storing and editing graphic images represented by digital data, includes a frame memory for storing pixel data representing graphic images including first and second graphic objects. The pixel data is stored at addresses, each being associated with one or more graphic fragment forming the first and second graphic objects. First and second addresses are respectively associated with those of the graphic fragments forming the first and second graphic objects. A memory controller controls writing and reading the pixel data to and from the frame memory. A fragment editor is provided to receive the pixel data read from the first address and modify the associated fragment with the received pixel data so as to form modified pixel data. An address detector detects the first address responsive to a request to read the pixel data from the first address and the second address responsive to a subsequent request to read pixel data from the second address. The detector compares the detected first and second addresses to identify an overlap of the first and second graphic objects. If an overlap is identified, the controller controls the writing of the modified pixel data to the first address before the reading of the pixel data from the second address.

Graphic system with read/write overlap detector

A method for improving the performance of a graphics system includes the steps of allocating appropriate pixels to slices of memory such that corresponding subsets of bits of neighboring pixels are allocated to different slices of memory, where `neighboring pixels` includes both consecutive pixels in a scan line, or pixels in consecutive scan lines. In addition, hardware is provided that allows for the individual memory slices to be independently accessed, thus allowed each slice to access data from a different 64 bit word in video memory during one video access period. Controllers which independently access the memory slices are advantageously totally time independent, to allow the most flexibility in the starting and finishing of the access of the memory slice. Performance is further gained by buffering of both the read and write requests to the video memory. Buffering requests allows reads and writes to neighboring locations to be merged to allow for the maximal bus utilization and minimizes the number of stalls in the video subsystem.

Method for providing improved graphics performance through atypical

A video subsystem of a computer processor is shown to include a graphics controller coupled to a video memory. A method for improving graphics performance for applications which use fewer bits per pixel than provided in the graphics subsystem includes the steps of rearranging the pixel and byte data in video memory such that corresponding bytes of different pixels are stored in different, simultaneously accessible locations of the video memory. With such an arrangement, accesses to video memory may be provided which utilize all of the available bytes of the video memory bus, thereby increasing the performance of the graphics operation. In addition, a graphics system having a plurality of independently operating memory controllers is shown to further improve graphics performance by ensuring that the video memory bus operates at full capacity.

Method for quickly painting and copying shallow pixels on a deep frame

An apparatus and method for storing pixel data in a video memory having a plurality of slices increases the performance of line drawing by ensuring that for a given pixel, neighboring pixels in neighboring scan lines are stored in separate slices of video memory. One embodiment of the invention includes the step of appending a number of offset bits to the end of each scan line, where the number of offset bits is less than the total number of bits contained in the plurality of slices. Another embodiment of the invention rearranges the pixels of every other scan line. Another embodiment adds an offset number of pixels which is equal to the number of pixels per slice times the number of slices, then alternates ordered pixels with rearranged pixels throughout successive scan lines. Performance is further increased by providing a plurality of memory controllers corresponding to the plurality of slices of memory which may operate asynchronously to interleave memory access commands. Therefore, during line draw operations successive pixels which reside in different slices of memory may be accessed in one command, and subsequent accesses may be interleaved to further increase the performance of line drawing operations.

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Sterling, MA, United States of America

Christopher C Gianos