Massana Research Limited

Christopher Bleakley

Brian Paul Murray

Vincent Berg

Jose Rodriguez

An address generation unit (AGU) and a digital signal processor (DSP) including such an AGU are disclosed. The AGU ( ) has a register file ( ) providing order (R), stage (S), and displacement (N) values to a digital addressing unit (DAU) ( ) for performing one of eight addressing operations. The register file provides an input (X) to the DAU and receives an output (Y) from the DAU. Within the DAU ( ), selection multiplexers ( ) select full adder outputs to provide Y, or bit-select from adders and the input (X) to provide Y. For a radix- operation, most significant bits (MSBs) are taken from the input (X), middle bits are taken from the output of a first adder (adder ), and the least significant bits (LSBs) are taken from the output of a second adder (adder ) if there is a carry out from the first adder. The AGU may also include bit reverse blocks connected at both the input and output of an adder. The DSP includes a program control unit for delivering a control signal to the AGU for selection of a required addressing operation.

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Dublin, Ireland

Christopher Bleakley