Semiconductor Components Industries, LLC

Christopher Ben Bartholomeusz

Gang Chen

Anthony Gerard Russell

Gabor Reizik

A circuit generates an output voltage from an input voltage and includes a Pulse Width Modulation (PWM) controller. The PWM controller initiates a PWM pulse according to a first comparison that uses a Current Sense and Ramp (CSR) signal and an error signal. The PWM controller ends the PWM pulse according to a second comparison that uses the CSR signal and a threshold signal. The CSR signal is generated using a current sense signal and a ramp signal according to the input voltage. The error signal is generated from the output voltage and a reference voltage. In an embodiment, the circuit is one of a plurality of substantially identical modules, wherein one module is a master module. The master module generates an error signal used by each module. A clock input of each module is respectively connected to a clock output of another module to sequentially activate each of the modules.

Pulse width control for switching mode power converters

A drive circuit and a method for maintaining an operating state of the drive circuit. The drive circuit includes a capacitor connected to an inverting input terminal of an operational amplifier and to a terminal of a current sensitive load through a switch. The output of the operational amplifier is connected to a switching regulator which has an output terminal connected to another terminal of the current sensitive load. An energy storage element is connected to the inverting input terminal of the operational amplifier. Energy is stored in the energy storage element during a first portion of a PWM pulse which is used during a second portion of the PWM pulse to generate the error signal. A drive signal is generated from the error signal where the drive signal is used to generate a voltage that biases the current source during the second portion of the PWM pulse.

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San Jose, CA, United States of America

Christopher Ben Bartholomeusz