Cornell University

Christopher Batten

Helena Caminal

José F Martínez

Kailin Yang

Khalid Al-Hawaj

Amit Lal

A content-addressable processing engine, also referred to herein as CAPE, is provided. Processing-in-memory (PIM) architectures attempt to overcome the von Neumann bottleneck by combining computation and storage logic into a single component. CAPE provides a general-purpose PIM microarchitecture that provides acceleration of vector operations while being programmable with standard reduced instruction set computing (RISC) instructions, such as RISC-V instructions with standard vector extensions. CAPE can be implemented as a standalone core that specializes in associative computing, and that can be integrated in a tiled multicore chip alongside other types of compute engines. Certain embodiments of CAPE achieve average speedups of 14× (up to 254×) over an area-equivalent out-of-order processor core tile with three levels of caches across a diverse set of representative applications.

Content-addressable processing engine

A system, comprising: (i) an interposer layer; (ii) a circuit layer positioned on the interposer layer and comprising a plurality of sonically-enabled pads; and (iii) an interrogator layer positioned on the circuit layer and comprising a plurality of ultrasonic transducers configured to sonically interrogate the circuit layer; wherein the sonically-enabled pads are configured to generate an electrical signal in response to sonic interrogation from the interrogator layer, if the sonically-enabled pad is functional.

Sonic testing method, apparatus and applications

A content-addressable processing engine, also referred to herein as CAPE, is provided. Processing-in-memory (PIM) architectures attempt to overcome the von Neumann bottleneck by combining computation and storage logic into a single component. CAPE provides a general-purpose PIM microarchitecture that provides acceleration of vector operations while being programmable with standard reduced instruction set computing (RISC) instructions, such as RISC-V instructions with standard vector extensions. CAPE can be implemented as a standalone core that specializes in associative computing, and that can be integrated in a tiled multicore chip alongside other types of compute engines. Certain embodiments of CAPE achieve average speedups of 14&#xd7; (up to 254&#xd7;) over an area-equivalent out-of-order processor core tile with three levels of caches across a diverse set of representative applications.

Growing community of inventors

Ithaca, NY, United States of America

Christopher Batten