Texas Instruments Corporation

Christopher Barr

Donald Edward Steiss

Clive D Bittlestone

Joonsung Park

Peter Cumming

Srinadh Madhavapeddi

Alessandro Paglieri

Ramyanshu Datta

A computing device uses a recursive discrete Fourier transform (RDFT) engine to reduce time required by a frequency transform module, memory required to hold intermediate products, and/or computing resources used for the testing. In an embodiment the windowing function is integrated and processed simultaneously with the recursive DFT funcions. A frequency-bin power module is configured to determine the frequency bin within the set of frequency bins that has a greatest signal power at various levels of recursion.

On-chip spectral analysis using enhanced recursive discrete Fourier transforms

Methods and apparatus to test and compensate multi-channel digital-to-analog converters (DACs) are described. In some examples, a multi-channel digital-to-analog converter (DAC) and an error detector are implemented in an integrated circuit. The multi-channel DAC includes a first DAC channel configured to generate a first analog representation of a digital input signal, and a second DAC channel configured to generate a second analog representation of the digital input signal. The error detector is configured to compare the first analog representation and the second analog representation to generate a difference signal, and to output a signal indicative of whether the difference signal is greater than a predetermined threshold.

Methods and apparatus to test and compensate multi-channel digital-to-analog converters

A flip flop ( ) comprising a master stage ( ) comprising a first plurality of transistors ( ), wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain. The flip flop also comprises a slave stage ( ) comprising a second plurality of transistors ( ), wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain. For the flip flop, in a low power mode the flip flop is operable to receive a first voltage (V ) coupled to the selective conductive path for each of the first plurality of transistors. Also in the low power mode, the flip flop is operable to receive a second voltage (V ) coupled to the selective conductive path for each of the second plurality of transistors. Lastly, the second voltage is greater than the first voltage in the low power mode.

Flip flop with reduced leakage current

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Plano, TX, United States of America

Christopher Barr