Hewlett-Packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Christopher B Wilson

Daniel Alan Berkram

Dacheng Zhou

Christopher Allan Poirier

Carson Donahue Henrion

Corey W Wick

Ryan Barnhill

Ed Reynolds

Mark L Thoveson

Karen S Anderson

Hank Edwards

A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.

Comparator

An apparatus, system, and method for facilitating communication handing of a terminating communication, terminating or originating, at a mobile station. User preferences are entered and stored at a database. When a terminating communication is subsequently initiated, the stored preferences are accessed, and instructions are provided to the mobile station to cause communication termination in conformity with the stored preferences.

System and method for controlling handling of terminating a communication

A memory access strobe configuration system and process operable to generate a strobe signal having a selected phase. Based on the strobe signal, a write/read cycle using a first logic value at a memory location of a memory device generates a result logic value. The result logic value provided by the write/read cycle is compared to the first logic value. Where there is a mismatch between the result logic value and the first logic value, the phase of the strobe signal is updated. The process is then repeated using a strobe signal having the updated phase.

Memory access strobe configuration system and process

A serial interface apparatus comprises a driver for generating a differential communication signal and a pre-driver for driving the driver circuit. The pre-driver receives an input signal that alternates between VDD and ground and produces an output signal that alternates between a lower limit that is greater than ground and an upper limit that is less than VDD. The pre-driver comprises input circuitry and actuation circuitry, and the actuation circuitry comprises transistors of a single channel type.

Pre-driver circuit using transistors of a single channel type

In one embodiment, a pre-driver circuit comprises input circuitry connected to receive a digital input signal that alternates between an upper voltage rail and a lower voltage rail and to provide a first inverted signal that is an inversion of the digital input signal and a second inverted signal that is an inversion of the first inverted signal. The pre-driver circuit also includes actuation circuitry connected to be driven by the digital input signal, the first inverted signal, and the second inverted signal to produce a digital output signal that alternates between an upper limit that is less than the upper rail and a lower limit that is greater than the lower rail by at least an amount, wherein all transistors forming the actuation circuitry comprise a single channel type.

Pre-driver circuit and appparatus using same

In one embodiment, a clock divider for producing a signal having a fifty percent duty cycle includes signal modifier circuitry connected to provide a variable clock signal. Responsive to first and second control signals of the signal modifier circuitry having respective first values, the signal modifier circuitry modifies a differential clock signal that includes first and second complementary clock signals to produce the variable clock signal, which contains an extended clock phase in every Icycle, I being an integer. The clock divider also contains counting circuitry connected to change the value of an output signal each time I cycles of the variable clock signal are counted.

Fifty percent duty cycle clock divider circuit and method

In one embodiment, a ratio clock divider comprises circuitry for producing an input signal from a differential clock signal, part of which includes circuitry for extending a clock phase of the differential clock signal every Icycle to produce the input signal, I being an integer. The ratio clock divider also includes circuitry for dividing the frequency of the input signal by I to produce a divided clock signal. The divided clock signal has a frequency that equals the frequency of the differential clock signal divided by N, N being equal to I plus a fraction F.

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Atlanta, GA, United States of America

Christopher B Wilson