Intel Corporation

Kepler Computing Inc.

Christopher B Wilkerson

Sasikanth Manipatruni

Amrita Mathuriya

Rajeev Kumar Dokania

Zeshan A Chishti

Alaa R Alameldeen

Debo Olaosebikan

Shih-Lien L Lu

Vivek K De

Seth H Pugsley

Ren Wang

Zhe Wang

Binh Q Pham

Muhammad M Khellah

Ming Lei Zhang

Tanay Karnik

James W Tschanz

Andrew J Herdrich

Srikanth T Srinivasan

Antonio Gonzalez

Xavier Vera

Dz-Ching Ju

Javier Carretero Casado

Jaume Abella

Pedro Chaparro Monferrer

Robert G Blankenship

Raanan Sade

Anil Vasudevan

Vedaraman Geetha

Kingsum Chow

Shrikant M Shah

Patrick Lu

Nam Sung Kim

Chyi-Chang Miao

Keith A Bowman

Venkata Krishnan

Marshall A Millier

Janice C Lee

Peng-Fei Chuang

Wayne A Wong

Olivier Serres

Robert L Scott

Wei Liu

Youfeng Wu

Eugene Gorbatov

Wei Wu

Herbert H Hum

Aamer Jaleel

Jared Warner Stark, Iv

Ryan N Rakvic

Jaewoong Sim

James J Greensky

Mariette Awad

Karl I Taht

Tsung-Yuan Charles Tai

Hong Wang

Dinesh Somasekhar

Edward Thomas Grochowski

Sanjeev Kumar

John Thomas Shen

Deborah T Marr

Jaydeep P Kulkarni

John P Shen

Scott H Robinson

Jonathan Cannon Hall

Namakkal N Venkatesan

Bryan P Black

Nicholas D Wade

Jawad Nasrullah

Roger Gramunt

Edward A Brekelbaum

Gunjan H Pandya

Jack D Mills

Bibiche M Geuskens

Ganesh Venkatesh

Manjunath Shevgoor

Kelvin Kwan

Khun Ban

Jared W Stark

Bohuslav Rychlik

Prabhat Jain

Ilya Wagner

Samira M Khan

Nicolas G Mitri

Nicholas G Mitri

Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

Random swap injection

A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

3D stack of split graphics processing logic dies

A ferroelectric memory chiplet in a multi-dimensional packaging. The multi-dimensional packaging includes a first die comprising a switch and a first plurality of input-output transceivers. The multi-dimensional packaging includes a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers. The multi-dimensional packaging includes a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os. The dies are wafer-to-wafer bonded or coupled via micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate, or embedded multi-die interconnect bridge.

Ferroelectric memory chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer

Ferroelectric memory chiplet in a multi-dimensional packaging

Method and apparatus for heuristic-based power gating of non-CMOS logic and CMOS based logic

Method and apparatus for managing power in a multi-dimensional packaging

Method and apparatus for managing power of ferroelectric or paraelectric logic and CMOS based logic

Method and apparatus to process an instruction for a distributed logic having tightly coupled accelerator core and processor core in a multi-dimensional packaging

In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.

Branch prediction based on coherence operations in processors

Apparatus and method for endurance of non-volatile memory banks via wear leveling with linear indexing

Apparatus and method for endurance of non-volatile memory banks via wear leveling in a round robin fashion

Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging

Method and apparatus for cycle-by-cycle clock gating of ferroelectric or paraelectric logic and CMOS based logic

Method to segregate logic and memory into separate dies for thermal management in a multi-dimensional packaging

Apparatus and method for endurance of non-volatile memory banks via multi-level wear leveling

Growing community of inventors

Portland, OR, United States of America

Christopher B Wilkerson