Stmicroelectronics Asia Pacific Pte Limited

Christopher Anthony Aldrige

Ser Wah Oh

An efficient architecture for a rake combiner is disclosed, for constructively combining the desired multi-path signals from a Code-Division Multiple-Access (CDMA) based system, such as a Third-Generation Partnership Project (3GPP) Frequency Division Duplex (FDD) mode Wideband CDMA (W-CDMA) system, or an IS-95 CDMA system. The described rake combiner employs a single M-stage tap-delay line, an N+1 input adder, an arrangement of index offsets, pass gates, comparators and an M-stage counter to perform the combination, where M represents the delay spread in terms of symbol duration and N represents the number of rake fingers to be combined. The rake combiner architecture facilitates lowered resource requirements through use of a single tap-delay line in contrast to a conventional rake combiner which uses a series of M-stage tap-delay lines and an N input adder to perform the combination.

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Singapore, Singapore

Christopher Anthony Aldrige