Microsoft Technology Licensing, LLC

Christopher Anand Pattison

Helmut Gottfried Katzgraber

Matthias Troyer

Nicolas Guillaume Delfosse

Krysta Marie Svore

Srilatha Manne

Douglas M Carmean

Poulami Das

Damian Silvio Steiger

Michael Edward Beverland

Marcus Palmer Da Silva

A computing device, including memory, an accelerator device, and a processor. The processor may generate a plurality of data packs that each indicate an update to a variable of one or more variables of a combinatorial cost function. The processor may transmit the plurality of data packs to the accelerator device. The accelerator device may, for each data pack, retrieve a variable value of the variable indicated by the data pack and generate an updated variable value. The accelerator device may generate an updated cost function value based on the updated variable value. The accelerator device may be further configured to determine a transition probability using a Monte Carlo algorithm and may store the updated variable value and the updated cost function value with the transition probability. The accelerator device may output a final updated cost function value to the processor.

Accelerator for computing combinatorial cost function

A quantum computing device comprises a surface code lattice that includes l logical qubits, where l is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the l logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.

Geometry-based compression for quantum computing devices

A quantum computing device comprises at least one quantum register including l logical qubits, where l is a positive integer. The quantum computing device further includes a set of d decoder blocks coupled to the at least one quantum register, where d<2*l. In this way, the decoder blocks may share decoding requests generated by the logical qubits.

Systems for coupling decoders to quantum registers

A computing device is provided, including memory storing a cost function of a plurality of variables. The computing device may further include a processor configured to, for a stochastic simulation algorithm, compute a control parameter upper bound. The processor may compute a control parameter lower bound. The processor may compute a plurality of intermediate control parameter values within a control parameter range between the control parameter lower bound and the control parameter upper bound. The processor may compute an estimated minimum or an estimated maximum of the cost function using the stochastic simulation algorithm with the control parameter upper bound, the control parameter lower bound, and the plurality of intermediate control parameter values. A plurality of copies of the cost function may be simulated with a respective plurality of seed values.

Computing stochastic simulation control parameters

A computing device is provided, including a cluster update accelerator circuit configured to receive signals encoding a combinatorial cost function of a plurality of variables and a connectivity graph for the combinatorial cost function. In an energy sum phase, the cluster update accelerator circuit may determine a respective plurality of accumulated energy change values for the combinatorial cost function based at least in part on the connectivity graph. In an update phase, the cluster update accelerator circuit may determine a respective update indicator bit for each accumulated energy change value. In an encoder phase, based on the plurality of update indicator bits, the cluster update accelerator circuit may select a largest update-indicated cluster of the variables included in the connectivity graph. The cluster update accelerator circuit may output an instruction to update the variables included in the largest update-indicated cluster.

Cluster update accelerator circuit

A quantum computing system computes soft information quantifying an effect of soft noise on multiple rounds of a syndrome measurement that is output by a quantum measurement circuit. The soft noise arises due to imperfections in a readout device that introduce variability in repeated measurements of ancilla qubits and is distinct from quantum noise arising from bit-flips in data qubits that are indirectly measured by the ancilla qubits. The quantum computing system applying decoding logic to identify fault locations within the quantum measurement circuit based on the computed soft information.

Quantum error correction with realistic measurement data

A quantum computing device comprises at least one quantum register including a plurality of logical qubits. A compression engine is coupled to each logical qubit of the plurality of logical qubits. Each compression engine is configured to compress syndrome data. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.

Growing community of inventors

Seattle, WA, United States of America

Christopher Anand Pattison