Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Intel Corporation

Christopher Allan Poirier

Samuel D Naffziger

Christopher Jonathan Bostak

Dacheng Zhou

Ryan Barnhill

Ankush Varma

Daniel Alan Berkram

Eric J DeHaemer

Malini Krishnan Bhandaru

James R Vash

Ronny Lee Arnold

Scott P Bobholz

Eric S Fetzer

Monica C Wong-Chan

Joel D Lamb

James Ignowski

Christopher B Wilson

Kevin Liao

Shahram Ghahremani

Edward James Luckett

Examples disclosed herein relate to set-reset (SR) latch circuits and methods for manufacturing the same. In some of the disclosed examples, a SR latch circuit includes an inverter storage loop for storing state information and a set of p-channel field-effect transistors (PFETs) for control circuitry. The PFETs may include first and second PFETs connected to a first node of the inverter storage loop, and third and fourth PFETs connected to a second node of the inverter storage loop. Gate terminals of the first and fourth PFETs may be connected to a first control input, and gate terminals of the second and third PFETs may be connected to a second control input.

Set-reset latches

A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver.

Comparator

According to examples, an apparatus may include a field effect transistor (FET), a driver to receive an input signal and to output a driver output signal, and a gate to receive the input signal. The apparatus may also include a delay element to receive the driver output signal and to output a delayed signal to the gate after a delay from receipt of the driver output signal, in which the gate is to output a gate output signal to the FET in response to receipt of the input signal and the delayed signal, and in which receipt of the gate output signal by the FET drives the FET to provide a boost to the driver output signal.

Delayed boost of driver output signals

In one embodiment, the present invention includes a method for determining whether a number of stalled cores of a multicore processor is greater than a stall threshold. If so, a recommendation may be made that an operating frequency of system agent circuitry of the processor be increased. Then based on multiple recommendations, a candidate operating frequency of the system agent circuitry can be set. Other embodiments are described and claimed.

Dynamically controlling interconnect frequency in a processor

An apparatus comprising an integrated circuit on a VLSI die, and an embedded micro-controller constructed on the VLSI die, the micro-controller adapted to monitor and control the VLSI environment to optimize the integrated circuit operation. Another embodiment of the invention is directed to a method for monitoring and controlling an integrated circuit comprising providing an embedded micro-controller on a same VLSI die as the integrated circuit, monitoring and controlling a VLSI environment of the integrated circuit with the embedded micro-controller.

System for and method of controlling a VLSI environment

Devices and methods for managing power on a module are disclosed herein. In one embodiment, a module comprises a first die; a second die; and a power manager. The power manager monitors the power requirements of the first die and the second die and allocates power to the first die and the second die based on the power requirements.

Inter-die power manager and power management method

Systems and methods for maintaining performance of an integrated circuit are disclosed. One embodiment of a system may comprise a working power limit evaluator that determines a working power limit as a function of at least one performance factor associated with variations that affect performance of the integrated circuit. The system may further comprise a power management system that varies power of the integrated circuit based on the working power limit and an actual power of the integrated circuit to maintain a substantially constant performance.

Systems and methods for maintaining performance of an integrated circuit within a working power limit

A system and method that can be utilized to implement voltage adjustment (e.g., for an integrated circuit). In one embodiment, the system comprises a frequency generator that provides a clock signal having a frequency that varies based on an operating voltage. The system also includes a controller that provides a control signal to adjust the operating voltage based on adjustments to the frequency of the clock signal.

System and method to adjust voltage

The present invention is directed to a system and method for measuring a current in an integrated circuit comprising measuring a first output count from a first voltage controlled oscillator (VCO) using a first measurement voltage, simultaneously measuring a second output count from a second VCO using a second measurement voltage, and calculating the current in the integrated circuit using a voltage proportional to a difference between the first and second output counts.

System and method for measuring current

A method for calibrating a voltage controlled oscillator (VCO) comprising applying a plurality of known voltages to the input of a VCO, monitoring, for each of the voltages, an output count from the VCO over a set interval, and storing the output counts for each voltage. Also disclosed is a system for calibrating a voltage controlled oscillator (VCO) comprising a plurality of known voltages, wherein the known voltage are connectable to the VCO, and a controller coupled to the output of the VCO, wherein the controller maintains a calibration table of VCO output counts for selected voltage inputs.

Method and system for calibration of a voltage controlled oscillator (VCO)

A system and method for measuring integrated circuit processor power demand comprises calibrating one or more voltage controlled oscillators for use as ammeters, calibrating a calibration current source, wherein the calibration current source draws current through a inherent resistance, calibrating the inherent resistance, and interleaving said calibrations in time with calculating the processor power demand using a voltage that is measured across the inherent resistance.

Method for measuring integrated circuit processor power demand and associated system

A method of rapidly detecting data errors includes generating a reference syndrome from data bits in a data word, the reference syndrome having at least a first portion and a second portion, generating a partial error code from the data bits and the first portion of the reference syndrome, and initiating an error recovery procedure if the partial error code contains any true values.

Early error detection using ECC

A method and apparatus are provided for sensing and temporarily latching data signals from memory cells. According to one embodiment, data signals are sensed from memory cells and temporarily latched on an output signal. During a first phase of a clock cycle, multiple input bit-lines are precharged. Subsequently, a discharged input bit-line is sensed during a second phase of the clock cycle. Responsive to the sensing step, the output signal is set to a first state and maintained for at least one clock cycle. According to another embodiment, a multiple input bit-line detecting circuit includes multiple input bit-lines, precharge logic, and output logic. The multiple input bit-lines are configured to be coupled to a bit-line hierarchy of a memory device. The precharge logic is coupled to each of the input bit-lines and is configured to precharge each of the input bit-lines during a first phase of a clock cycle. The output logic is operatively coupled to the multiple input bit-lines to set an output signal to a first state and maintain the first state on the output signal for at least one clock cycle in response to one or more of the input bit-lines being discharged.

Growing community of inventors

Fort Collins, CO, United States of America

Christopher Allan Poirier