Stmicroelectronics Asia Pacific Pte Limited

National University of Singapore

Christopher Aldridge

Ser Wah Oh

Karthik Muralidhar

Mohamed Imtiyaz Iqbal

Wee Tiong Tan

Chong Yee Lee

Karthik Sathiavageeswaran

Mridula Pradhan

Chia Kwang Kang

Two preferred embodiments provide slot synchronization of an initial cell search. Two Finite Impulse Response (FIR) filters are used to correlate the synchronization codes transmitted in the downlink (forward link). A sign bit is taken after the first FIR to significantly reduce the hardware requirements for the second FIR, and thus the whole system. The correlated results from the second FIR can be further processed using two different algorithms. The first adds a square operation to the correlated results whilst the second takes the magnitude before passing to the next stage. Regardless of which algorithm is adopted, the results are accumulated (I and Q), instead of averaged, and stored in a memory location for each successive correlation over the same location in different slots. The physical-layer processor (PLP) then reads the accumulated results from the memory location and searches for the peak position corresponding to the slot boundary.

High performance W-CDMA slot synchronisation for initial cell search with reduced hardware

The range R of effective bits (those containing information) within the N bit output(s) from an inner modem is determined and employed to select the M soft bits passed to a channel decoder, thereby avoiding underflow or overflow degrading the channel decoder performance. The average and standard deviation of 1P values for a base-two logarithm of the N bit output are used to determine the range R of effective bits, with the N bits shifted and clipped based on the computed value of R so that the M most significant bits from that range R are passed to the channel decoder.

Method to adaptively scale the input to a channel decoder

A method of dividing, in a micro computer unit (MCU), a first binary number (N), having a first number of significant bits, by a second binary number (D), having a second number of significant bits, produces an integer result (Y). The method includes: determining the difference (K) between the first and second numbers of significant bits; aligning the most significant bits (MSBs) of N and D by shifting the bits of D, by K bit positions, such that its MSB occupies the same relative bit position as the MSB of N; repeating K times: multiplying Y by 2; dividing D by 2; and, if N is greater than or equal to D: increasing Y by 1; setting N equal to N&#x2212;D.

Divider apparatus and associated method

A low-power receiver architecture of use in direct sequence spread spectrum communications system receivers, such as in a code division multiple access system, is provided. The receiver employs analog correlation, wherein its analog-digital, converters are able to operate at the system symbol rate, and the requirement for finite impulse response filters is obviated. The low-power receiver architecture is also applicable as a front-end structure for multiple-mode receivers.

Low-power code division multiple access receiver

A method of calculating a Cyclic Redundancy Check (CRC) value for a multi-bit input data word, using a defined generator polynomial is disclosed. The method includes the steps of: serially shifting at least a portion of the input data word into a register; XORing the contents of the register with the generator polynomial if the LSB of the register is '1'; shifting the contents of the register right by one position; shifting into the MSB position of the register a new bit of the input data word, having been XORed with the LSB of the register; repeating the previous step for all message data bits; shifting into the register a number of '0's equal to the length of the generator polynomial; reading from the register the calculated CRC value. Apparatus for performing the method is also disclosed.

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Singapore, Singapore

Christopher Aldridge