3com Corporation

3com Technologies

Christopher Alan Walker

David J Law

Nicholas Mark Stapleton

Alan R Poulter

Quang T Tran

Sharon L Wiles

Paul J Moran

Daniel M O'Keeffe

Kevin Loughran

Justin A Drummond-Murray

Edward Turner

Patrick Michael Overs

Michael Joseph Gleeson

Robin Parry

Christopher Byham

Steven Brewer

David R Smith

David Wright

For each metered flow in a network unit there is a memory entry which defines a time stamp and a rate parameter. When a packet in the respective flow arrives, the time of arrival is compared with the time stamp. If the time of arrival is before the time stamp the packet is discarded. If the packet arrives after the date stamp, it is allowed to proceed and a new time stamp is computed in accordance with the rate parameter. One exemplary computation adds to the time stamp a time interval obtained by dividing the size of the packet by the rate parameter and preferably subtracting from the quotient the time interval between the arrival time and the previous time stamp.

Packet metering in high-speed network units

A connecting unit for use in a system comprising a 'stack' of network communication units having a cascade connection has three ports having lines for forwarding and receiving data packets and for forwarding and receiving control messages. The connecting unit increments a first signal value defining an identification number received by way of a control message at a first port, provides the received signal value by way of a control message to the third port and provides the incremented signal value by way of a control message to the second port. The connecting unit also receives a second signal value defining an active unit count by way of a control message at the first port and provides the second signal value, incremented or not in dependence on a control message received at the third port, in a control message at the second port. The first signal values (UnitIDs) are used to establish the numbering of the units in the stack and the second signal values are used to compute a count of the 'active' units in the stack.

Cascade architecture and operation for packet-based communication systems

A control device for a unit in a cascade connection of network units includes control logic which increments a count of active units and passes the count to the next control device. The count is initiated and terminated by an absence of control messages at the down port and up port respectively. The incremented count is passed up the cascade and a final count is passed down the cascade.

Cascade control architecture and operation for packet-based communication systems

A stackable network unit comprises a 'down' port and an 'up' port, an arbitration path for data packets from the down port to the up port, a repeat path for data packets from the up port to the down port, a link detector for detecting tile absence of another operative unit connected to the down port to cause data packets on the return pat to bypass the down port and proceed on the arbitration path and for detecting the absence of another operative unit connected to the up port to cause data packets on the arbitration path to bypass the up port and proceed on the repeat path.

Method and apparatus for configuration of stackable units in packet-based communications systems

A communications apparatus comprising a plurality of communication devices each having a plurality of ports and a data bus interconnecting the plurality of units, wherein each device is provided with means enabling the device to detect automatically its position on the data bus.

Communication device with circuitry to promote cascade series connection including identification of device position in the series and sensing the end device in the series

A data network hub unit is stackable with other such units to constitute a hub in which each of the units can supply data packets to network data destinations and receive data packets from network data sources, and to form a closed data transmission ring which enables packets received at any unit to be transmitted from any other unit. The hub unit includes arbitration control means responsive to packet headers circulating on said ring. The arbitration control means is operative: (i) when the hub unit acts a master unit to supply data packets, to modify data packets to provide them each with an arbitration header which includes a grant field, a request priority field, capable of indicating various different level of priority, and a grant priority field; (ii) when the hub unit is acting as the master unit and has no more data packets to supply to the ring, to respond to an arbitration header which has a set priority field by setting the grant field and setting the grant priority field; (iii) when the hub unit is not the master unit but has data packets to place on the ring, to respond to arbitration headers by setting a priority field; and (iv) when the hub unit is not the master unit but has data packets to send, to respond to an arbitration header which has the grant field set and a grant priority field indicating a priority level corresponding to the priority requested by this unit to become the master unit.

Hub system with ring arbitration

A clock selector circuit for selecting a single output clock signal from a multiplicity of input clock signals, each constituted by transitions between binary states, comprises a multiplicity of D-bistables each having a clock input coupled to receive the respective one of the input clock signals, a D-input coupled to receive a hold signal common to the bistables, and an output for providing a respective hold signal. A first multiplexer has inputs coupled to receive the respective input clock signals and is operative to select in response to the selection signal one of said input signals. A second multiplexer has inputs coupled to receive the respective hold signals and is operative to select in response to the selection signal the hold signal corresponding to the clock signal selected by the first multiplexer. A gate is coupled to receive both the clock signal selected by the first multiplexer and the hold signal selected by the second multiplexer and asserts an output whichever of the input signals to the gate may be asserted. The assertion of the common hold signal precedes a chance in state of the selection signal and endures at least until all the hold signals have been asserted and a change in state of the selection signal has occurred. The circuit facilitates glitch-free clock multiplexing.

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Watford, United Kingdom

Christopher Alan Walker