National Semiconductor Corporation

Christopher Alan Menkus

Robert Callaghan Taft

Ols Hidri

Maria Rosaria Tursi

Andreas Tuechler

Valerie Pons

A clock receiver for an integrated circuit includes duty-cycle correction capabilities based on monitoring an average value associated with an internally generated clock signal. An active adjustment circuit within the clock receiver provides correction to each leg of the differential clock signal based on two correction signals. The correction signals are derived from a comparison of the average value associated with the internal clock signal with a target voltage. The target voltage is based on a trip-point of an inverter stage in a logic stage that is driven by the internal clock signal. The closed loop control of the correction signals adjusts the average value of the internal clock signal until it is substantially equal to the target voltage. By straddling the internal clock signal about the trip-point of the inverter stage, the duty-cycle associated with the internal clock signal is adjusted to substantially a 50% duty cycle.

Duty-cycle correction for clock receiver

An on-chip resistor is calibrated with a sense circuit that compares a resistance associated with an off-chip resistor to the on-chip resistor via a current-mirror circuit and a comparator. A digital counter circuit evaluates the comparison and adjusts its count such that a variable digital control signal is provided to the on-chip resistor circuit. During the calibration of the on-chip resistor circuit, the resistance of the on-chip resistor can be matched to the resistance of the off-chip resistor according to a scaling factor (e.g., 1&#xd7;, 2&#xd7;, 2.5&#xd7;, 10&#xd7;, etc.) as may be desired. Once the resistance associated with the on-chip resistor circuit is sufficiently adjusted, another on-chip resistor (e.g., a terminating resistor of another circuit) can be adjusted from the counter value. Various other circuits can be disabled during the calibration of the on-chip resistor such that additional sources of error (e.g., supply variation, ground bounce, noise, etc.) are minimized.

On-chip resistor calibration apparatus and method

A circuit for calibrating a coarse channel circuit in a folding analog-to-digital converter circuit. A reference value is input to the coarse channel circuit and an output of the coarse channel circuit is sensed. A parameter of the coarse channel circuit is adjusted until the coarse channel circuit is successfully calibrated.

Coarse channel calibration for folding ADC architectures

A reference voltage is generated between a first node and a second node. A resistive element and a junction device are coupled in series between the first node and the second node. The junction device includes a junction between dissimilar materials, and has a negative temperature coefficient. First and second current sources route respective first and second bias currents to the resistive element and to the junction device. Routing is such that a resulting first branch current through the resistive element is generally not equal to a resulting second branch current through the junction device. The second bias current depends less on manufacturing process variation than the first bias current, and the second branch current can contain more of it, for less dependence on process. The second bias current can be generated by a source that uses the generated reference voltage as a reference.

Generating reference voltages

A time interleaved ADC system includes a delay circuit that has a dynamically adjusted speed to achieve uniformly spaced sampling intervals. The adjustment control circuit monitors the sampling pulses associated with sampling time instant for each ADC, and provides one or more control signals to the delay circuit. In one example, the adjustment control circuit employs a phase detector circuit, an integrator circuit, and a dynamic biasing circuit. In this example, the phase detector circuit evaluates the sampling pulses to generate control signals for the integrator circuit, which generates signals that are utilized by the dynamic biasing circuit to adjust the delays associated with the delay circuit. The relative positions of the sampling pulses are controlled by adjusting the delay in the delay circuit.

Accurate sampling technique for ADC

An ADC circuit includes a multiplexer, a calibration circuit, one or more ADC banks, and a calibration ladder, all on an integrated circuit. The calibration resistor ladder is enabled during a calibration phase, and disabled during normal operation. When enabled, the calibration resistor ladder provides a calibration reference signal. Also, the multiplexer provides the calibration reference signal to one or more ADC banks during a calibration phase, and provides an analog input signal to the ADC banks otherwise. The calibration circuit is arranged to provide one or more adjustment signals to the ADC banks to calibrate the ADC banks in response to one or more comparator output signals from the ADC banks.

Apparatus and method for on-chip ADC calibration

A method and circuit for improving linearity of a folding or flash analog-digital-converter (ADC) circuit. Averaging resistors connect outputs of each of a bank of first pre-amplifiers. A series adjustment resistor is placed between each node connecting the output of a first bank pre-amplifier and the associated averaging resistor, and the input of each of a second bank pre-amplifier. An adjustment current is injected through the adjustment resistor during a calibration. A permanent value for adjustment current is determined such that an effect of offset errors is substantially minimized.

ADC linearity improvement

A method and circuit for terminating a pre-amplification array for stable linearity of a folding or flash analog-digital-converter (ADC) circuit over a temperature range. Termination resistors with pre-selected temperature coefficients are coupled between outputs of a first and a last amplifier of an amplifier bank in an averaged pre-amplification stage and a termination voltage source. The termination resistors and the termination voltage provide a current that compensates temperature dependent changes in the current flowing from other amplifiers outputs towards the output of the first and last amplifiers stabilizing linearity when temperature changes. Multiple termination resistors with different temperature coefficients may be employed to better approximate the desired temperature coefficient for optimum performance.

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Munich, Germany

Christopher Alan Menkus