Oracle America, Inc.

Sun Microsystems, Inc.

Qualcomm Incorporated

Oracle International Corporation

Christopher A Vick

Michael H Paleczny

Olaf Manczak

Gregory M Wright

Jay R Freeman

Phyllis E Gustafson

Clifford N Click

Yuguang Wu

Mario I Wolczko

Bin Wang

Lawrence G Votta

Mehrdad Mohammad H Reshadi

Miguel Angel Lujan Moreno

Mark S Moir

Peter B Kessler

Sudha Anil Kumar Gathala

Andres Valencia

Bo Yang

Anand S Gupta

Andrey Ermolinskiy

Ashok Halambi

Dinakar Dhurjati

Minjang Kim

Eric C Lalonde

Miguel-Angel Lujan Moreno

The aspects enable a processor to concurrently execute a first serial language code (e.g., HTML) embedding a second serial language code (e.g., JAVASCRIPT&#xae;) during a page load operation by a browser. A parser parses the first serial language code until a segment of the embedded second serial language code is encountered. The segment of embedded second serial language code is extracted for execution by an execution engine, which proceeds concurrently with speculative parsing of the first serial language code. Code generated by execution of second serial language code is evaluated to determine if it is well formed, and a partial rollback and re-parsing of the first serial language code is performed if the code is not well formed.

Concurrent parsing and processing of serial languages

Mobile computing devices may be configured to compile and execute portions of a general purpose software application in an auxiliary processor (e.g., a DSP) of a multiprocessor system by reading and writing information to a shared memory. A first process (P1) on the applications processor may request address negotiation with a second process (P2) on the auxiliary processor, obtain a first address map from a first operating system, and send the first address map to the auxiliary processor. The second process (P2) may receive the first address map, obtain a second address map from a second operating system, identify matching addresses in the first and second address maps, store the matching addresses as common virtual addresses, and send the common virtual addresses back to the applications processor. The first and second processes (i.e., P1 and P2) may each use the common virtual addresses to map physical pages to the memory.

Dynamic address negotiation for shared memory regions in heterogenous multiprocessor systems

The various aspects leverage the novel observation that the number of call sites in code is directly correlated with the code's compile time and provide methods implemented by a compiler operating on a computing device (e.g., a smartphone) for performing inline throttling based on a projected number of call sites in the code that would exist after performing inline expansion. The various aspects enable the compiler to improve the performance of the generated code by aggressive inlining while carefully managing increases in compile time, thereby decreasing the power required to compile the code while increasing performance of the computing device. Thus, by inlining enough call sites to reduce the costs of handling calls while accounting for the costs of inlining, the various aspects provide for an effective balance of short compile times and effective code performance.

Method for controlling inlining in a code generator

Methods, devices, and systems for automatically determining how an application program may be partitioned and offloaded for execution by a general purpose applications processor and an auxiliary processor (e.g., a DSP, GPU, etc.) within a mobile device. The mobile device may determine the portions of the application code that are best suited for execution on the auxiliary processor based on pattern-matching of directed acyclic graphs (DAGS). In particular, the mobile device may identify one or more patterns in the code, particularly in a data flow graph of the code, comparing each identified code pattern to predefined graph patterns known to have a certain benefit when executed on the auxiliary processor (e.g., a DSP). The mobile device may determine the costs and/or benefits of executing the portions of code on the auxiliary processor, and may offload portions that have low costs and/or high benefits related to the auxiliary processor.

Efficient directed acyclic graph pattern matching to enable code partitioning and execution on heterogeneous processor cores

The various aspects provide a dynamic compilation framework that includes a machine-independent optimization module operating on a computing device and methods for optimizing code with the machine-independent optimization module using a single, combined-forwards-backwards pass of the code. In the various aspects, the machine-independent optimization module may generate a graph of nodes from the IR, optimize nodes in the graph using forwards and backwards optimizations, and propagating the forwards and backwards optimizations to nodes in a bounded subgraph recognized or defined based on the position of the node currently being optimized. In the various aspects, the machine-independent optimization module may optimize the graph by performing forwards and/or backwards optimizations during a single pass through the graph, thereby achieving an effective degree of optimization and shorter overall compile times. Thus, the various aspects may provide a global optimization framework for dynamic compilers that is faster and more efficient than existing solutions.

Fast, combined forwards-backwards pass global optimization framework for dynamic compilers

In the various aspects, a virtual machine operating at the machine layer may use power consumption models to partition object code into portions, identify the relative power efficiencies of the mobile device processors for the various code portions, and route the code portions to the mobile device processors that can perform the operations using the least amount of energy. A dynamic binary translator process may translate the object code portions into an instruction set language supported by the hardware component identified as being preferred. The code portions may be executed and the amount of power consumed may be measured, with the measurements used to generate and/or update performance and power consumption models.

Power consumption optimized translation of object code partitioned for hardware component based on identified operations

One embodiment of the present invention provides a system that facilitates precise exception semantics for a virtual machine. During operation, the system executes a program in the virtual machine using a processor that includes a gated store buffer that stores values to be written to a memory. This gated store buffer is configured to delay a store to the memory until after a speculatively-optimized region of the program commits. The processor signals an exception when it detects that a load following the store is attempting to access the same memory region being written by the store prior to the commitment of the speculatively-optimized region.

Facilitating gated stores without data bypass

The aspects enable a computing device to allocate memory space to variables during runtime compilation of a software application. A compiler may be modified to identify operations that can be performed on either a main pipe or an alternative pipe, identify chains of related operations that can be performed on either the main pipe or the alternative pipe, identify points in the execution of code at which the number of live values will exceed the number of registers, and choosing a chain of operations as a candidate to be moved to the alternative pipe in order to reduce the number of live values at identified points in the execution of code. The entire chosen chain of operations may be moved to the alternative pipe. The alternative pipe may perform the computations and return the results to the main pipe for execution.

Method and apparatus for register spill minimization

The aspects enable a computing device to allocate memory space to variables during runtime compilation of a software application. A first variable associated with a code segment within code being compiled may be identified and assigned a priority tag. A second variable associated with another code segment within the code being compiled may also be assigned a priority tag. A determination may be made regarding whether the first and second variables are contemporaneously live during execution, and whether legal storage location sets for the first and second variables overlap. The assigned priority tags may be used for assigning storage locations to the first and second variables based on the determination.

Method and apparatus for avoiding register interference

In the various aspects, virtualization techniques may be used to reduce the amount of power consumed by execution of applications by power-optimizing the code prior to execution. A dynamic binary translator operating at the machine layer may use a power consumption model to identify code segments that can benefit from optimization and to perform an instruction-sequence to instruction-sequence translation of object code to generate power-optimized object code. Execution hardware may be instrumented with additional circuitry to measure the power consumption characteristics of executing code. The power consumption models may be updated and object code may be regenerated based on the measured the power consumption characteristics of previously executed code. In an aspect, power optimization may be accomplished when the computing device is connected to a battery charger.

Dynamic power optimization for computing devices

One embodiment provides a system that protects translated guest program code in a virtual machine that supports self-modifying program code. While executing a guest program in the virtual machine, the system uses a guest shadow page table associated with the guest program and the virtual machine to map a virtual memory page for the guest program to a physical memory page on the host computing device. The system then uses a dynamic compiler to translate guest program code in the virtual memory page into translated guest program code (e.g., native program instructions for the computing device). During compilation, the dynamic compiler stores in a compiler shadow page table and the guest shadow page table information that tracks whether the guest program code in the virtual memory page has been translated. The compiler subsequently uses the information stored in the guest shadow page table to detect attempts to modify the contents of the virtual memory page. Upon detecting such an attempt, the system invalidates the translated guest program code associated with the virtual memory page.

Method and apparatus for protecting translated code in a virtual machine

One embodiment of the present invention provides a system that improves program performance by enregistering memory locations. During operation, the system receives program object code which has been generated to use a specified number of registers that are available for a given target hardware implementation. Next, the system translates this object code to execute on a second hardware implementation which includes more registers than the first hardware implementation. The system uses these additional registers to improve the performance of the translated object code for the second hardware implementation. More specifically, the system identifies a memory access in the object code, and then rewrites an instruction associated with this memory access to access an available register instead of the original target memory location. To preserve program semantics, the system subsequently moderates accesses to the memory location to ensure that no threads access a stale value in the enregistered memory location.

Method and apparatus for enregistering memory locations

A method for memory protection in a multiprocessor system, involving receiving a request at a first carrier to perform a memory operation at a memory address, wherein the first carrier receives the request from a processor, determining by the first carrier whether the processor is permitted to access memory at the memory address using a carrier identification (ID) of a second carrier, wherein the second carrier is associated with a memory controller used to access the memory, and sending the request to the second carrier, if the processor is permitted to access the memory.

Method and system for memory protection by processor carrier based access control

A method for executing an application on multiple nodes includes synchronizing a first clock of a first node and a second clock of a second node, configuring a first hypervisor on the first node to execute a first application domain and a first privileged domain, and configuring a second hypervisor on the second node to execute a second application domain and a second privileged domain. Configuring the hypervisor includes allocating a first number of cycles of the first clock to the first privileged domain. Configuring the second hypervisor includes allocating the first number of cycles of the first clock to the second privileged domain. The method further includes executing the application in the first application domain and the second application domain. The first application domain and the second application domain execute semi-synchronously and the first privileged domain and the second privileged domain execute semi-synchronously.

Method and system for coordinating hypervisor scheduling

The aspects enable a processor to concurrently execute markup language code (e.g., HTML) having embedded scripting language code (e.g., JAVASCRIPT&#xae;) during a page load operation by a browser. A markup language parser parses markup language code until embedded scripting language code is encountered. The segment of embedded scripting language code is extracted for execution by a scripting language engine which proceeds concurrently with speculative parsing of the markup language code. Markup language code generated by execution of scripting language code is evaluated to determine if it is well formed, and a partial rollback of the markup language parse and re-parsing of portions of the markup language code is accomplished if not. Concurrent parsing of markup language code and execution of scripting language code, with partial roll back of the parsing process when necessary, continues until all markup language code has been parsed and all scripting language code has been executed.

Growing community of inventors

San Jose, CA, United States of America

Christopher A Vick