At+t Corp.

Lucent Technologies Inc.

At&t Bell Laboratories

L-3 Communications Corporation

Christopher A Stanziola

Richard Robert Shively

John M Segelken

Robert Raymond Miller, Ii

Ranjan V Sonalkar

Jerry Hutchison

Allen L Gorin

Patrick A Makofsky

Neal C Oliver

Nancy Morton

Lesley J Wu

Lesley J-y Wu

Methods and systems are described to allow for the parallel processing of packets and other subsets of data that are to be delivered in order after the completion of the parallel processing. The methods and systems may process packets and subsets of data that may vary in size by orders of magnitude. The packets may be transmitted and/or received over data transmission networks that may be orders of magnitude faster than the processing speeds of the parallel processors. Entire packets or subsets of data may be allocated to individual processing units without segmenting the packets between the processing units. A count value may be inserted as metadata to received packets in order to indicate a relative order of arrival. The metadata may be utilized by a multiplexor at the output of the parallel processing units in order to maintain in-sequence delivery of the processed packets.

Systems and methods for multicore processing of data with in-sequence delivery

In an arrangement where an incoming QPSK signal contains a PRN every N frames, oscillator synchronization is achieved via control signals that are developed from the PRN frame by rotating the vectors derived from demodulated received signal, applying a complex tracking filter to the results, averaging the results, performing phase accumulation, and developing an analog voltage to be applied to a voltage controlled oscillator through D/A conversion.

Timing recovery for DMT-based DSL modems

The number of circuit path crossover points on boards mounting plural connected multichip modules is substantially reduced over the number that would otherwise be required. For 4-sided modules and boards, the modules are arranged on the board in such a way that their inter-connecting north-east-south-west ports are successively reordered to N-S-E-W. Additionally, further advantage in reducing crossover vias may be gained by combining the reordering with a phased rotation of the modules from their nominal congruent board position. For the 4-sided module, these expedients virtually eliminate crossover vias between the east and west ports. It also provides for all MCMs a ready common bus structure located at a common interior area of the mounting board, to which the E- and W-ports are oriented. The invention is applicable to a class of multi-sided, multi-chip modules on boards with a like number of sides.

Reduced inter-module circuit path crossovers on circuit boards mounting

A system is described for arraying multi-device processing nodes in a 3-dimensional computing architecture and for flexibly connecting their ports. The topology of each processing node is of a fixed and constant physical geometry. The nodes may comprise a digital signal processor chip, a static RAM, and a communications and network controller. The nodes are mounted on boards. Selective connection of ports of each board to ports of another adjacent board is effected by a routing and spacer element having internal routing paths.

Stacked board assembly for computing machines, including routing boards

An interconnection scheme among the processing elements ('PEs') of a multiprocessor computing architecture realizes, through PE reconfiguration, both fault tolerance and a wide variety of different processing topologies including binary trees and linear systolic arrays. By using a novel variant on a tree expansion scheme, the invention also allows for arbitrary up-sizing of the PE count to build virtually any size of tree network, with each size exhibiting same high degree of fault tolerance and reconfigurability. The invention may be practiced with 4-port PEs arrayed in a module comprising a 4.times.4 board-mounted PE lattice. Each PE has four physical ports, which connect to the similar ports of its lattice neighbors. Each PE has an internal capability to be configured to route signals to or from any of its neighbors. Thus, for tree topologies, any of the four neighbors of a given PE may be selected as the parent of the given PE; and any or all of the remaining three neighboring PEs may be selected as the child(ren) PEs. The PE ports are configured under the control of a remote host, which establishes an initial desired PE topology. The operability of the PEs is tested, and information on faulty PEs or communications paths is used to enable or disable nodes as necessary by revising the PE port configurations. The nodes thus are reorganized and can run or continue running, on a degraded basis.

Reconfigurable signal processor

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Hyde Park, NY, United States of America

Christopher A Stanziola