Advanced Micro Devices Corporation

Globalfoundries Inc.

Asml Netherlands B.v.

Christopher A Spence

Todd P Lukanc

Luigi Capodieci

Stephen C Horne

John Christian Holst

Richard K Klein

Asim A Selcuk

Raymond T Lee

Hung-Eil Kim

Nicholas John Kepler

Cyrus E Tabery

Carl P Babcock

Chris Haidinyak

Craig S Sander

Sarah McGowan

Joerg Reiss

Zoran Krivokapic

Anna Maria Minvielle

Regina Tien Schmidt

Bhanwar Singh

Harry Jay Levinson

Marina V Plat

Duan-Fu Stephen Hsu

Jean Y Yang

Guoxiang Ning

Robert John Socha

Khanh B Nguyen

Yi Zou

Kouros Ghandehari

Paul Willard Ackmann

Chin Teong Lim

Jing Su

Jun Tao

Fan Piao

Eun-Joo Lee

Yu Cao

A method for training a machine learning model to generate a characteristic pattern, the method includes obtaining training data associated with a reference feature in a reference image. The training data includes (i) location data of each portion of the reference feature, and (ii) a presence value indicating whether the portion of the reference feature is located within a reference assist feature generated for the reference feature. The method includes training the machine learning model to predict a presence value based on the actual presence value in the training data. The predicted presence value indicates whether a portion of a feature (e.g., a skeleton point on a skeleton of a contour of the feature) is to be covered by an assist feature. The training is performed based on the training data such that a metric between a predicted presence value and the presence value is minimized.

Machine learning based subresolution assist feature placement

A method of controlling an imaging process uses a qualified optical proximity correction (OPC) model, the process including obtaining an OPC model that is configured to model the behavior of OPC modifications to a pre-OPC design in a process for forming a pattern on a substrate using a post-OPC design in a patterning process, using the patterning process in a manufacturing environment, collecting process control data in substrates patterned using the patterning process in the manufacturing environment, storing the collected process control data in a database, analyzing, by a hardware computer system, the stored, collected process control data to verify that the OPC model is correcting pattern features within a selected threshold, and for pattern features falling outside the selected threshold, determining a modification to the imaging process to correct imaging errors.

Measurement method and apparatus

A method includes obtaining a sub-layout having an area that is a performance limiting spot, adjusting colors of patterns in the area, and determining whether the area is still a performance limiting spot. Another method includes decomposing patterns in a design layout into multiple sub-layouts; determining for at least one area in one of the sub-layouts, the likelihood of that a figure of merit is beyond its allowed range; and if the likelihood is above a threshold, that one sub-layout has a performance limiting spot. Another method includes: obtaining a design layout having a first group of patterns and a second group of patterns, wherein colors of the first group of patterns are not allowed to change and colors of the second group of patterns are allowed to change; and co-optimizing at least the first group of patterns, the second group of patterns and an illumination of a lithographic apparatus.

Coloring aware optimization

A method and apparatus for an efficient optical proximity correction (OPC) repair flow is disclosed. Embodiments may include receiving an input data stream of an integrated circuit (IC) design layout, performing one or more iterations of an OPC step and a layout polishing step on the input data stream, and performing a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value. Additional embodiments may include performing a pattern insertion process cross-linked with the OPC step, the pattern insertion process being a base optical rule check (ORC) process.

Efficient optical proximity correction repair flow method and apparatus

A method includes receiving optical profiles for a plurality of design target features associated with an integrated circuit device and optical profiles for a plurality of test features. An optical proximity correction (OPC) model including a plurality of terms is defined. Each term relates to at least one parameter in the optical profiles. A subset of the model terms is identified as being priority terms. Parameters of the optical profiles of the test features are matched to parameters of the optical profiles of the design target features using the priority terms to generate a set of matched test features. A metrology request is generated to collect metrology data from a test wafer having formed thereon at least a first subset of the matched test features and a second subset of the design target features.

Method and apparatus for optimizing an optical proximity correction model

A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques

A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.

System and method for designing an integrated circuit device

A method of producing a layout representation corresponding to an integrated circuit (IC) device design can include generating an initial layout representation in accordance with a predetermined set of design rules and simulating how structures within the initial layout representation will pattern on a wafer. Based on the simulation, portions of the layout representation, which include structures demonstrating poor manufacturability and/or portions of the layout representation in which extra manufacturability margin is present, can be identified. Portions of the layout representation including structures demonstrating poor manufacturability and/or in which extra manufacturability margin is present can be modified to optimize the layout representation.

Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin

A method of generating a metrology recipe includes identifying regions of interest within a device layout. A coordinate list, which corresponds to the identified regions of interest, can be provided and used to create a clipped layout, which can be represented by a clipped layout data file. The clipped layout data file and corresponding coordinate list can be provided and converted into a metrology recipe for guiding one or more metrology instruments in testing a processed wafer and/or reticle. The experimental metrology results received in response to the metrology request can be linked to corresponding design data and simulation data and stored in a queriable database system.

Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results

A method of producing design rules including generating a plurality of parametrically varying geometric layouts and simulating how each geometric layout will pattern on a wafer. Edges of structures within the simulated geometric layouts can be classified based on manufacturability and design rules can be created to disallow layouts demonstrating poor manufacturability.

System and method for design rule creation and selection

A method of evaluating a wafer structure formation process includes extracting the outline of an actual mask pattern, and simulating a lithographic process using the actual mask pattern to obtain a simulated wafer structure. The extracting the outline of the actual mask pattern may include, for example, imaging the actual mask using a scanning electron microscope (SEM). A second simulated wafer structure may also be obtained, by simulating the lithographic process using the ideal mask pattern design that was used in producing the actual mask pattern. Thus the relative contribution of mask pattern effects to overall wafer proximity effects may be evaluated by comparing the two simulated wafer structures, either with each other or against a benchmark such as a desired, ideal structure. This information may then be used to generate optical proximity correction (OPC) mask designs which compensate for mask patterning errors and give better wafer performance. The simulated wafer structures may be overlaid upon one another to allow for a direct comparison and full analysis of CD variations.

Method for evaluation of reticle image using aerial image simulator

The invention includes an apparatus and a method of manufacturing such apparatus including the steps of: forming a layer to be patterned, forming a photosensitive layer over the layer to be patterned, patterning the photosensitive layer to form a pattern including a horizontal line and a vertical line without a space therebetween, transferring the pattern to the layer to be patterned, forming a second photosensitive layer over the pattern, patterning the second photosensitive layer to form a second pattern including a space aligned between the horizontal line and the vertical line, and transferring the second pattern to the layer to be patterned to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a width dimension achievable at a resolution limit of lithography.

Predefined critical spaces in IC patterning to reduce line end pull back

A system and method for generating an illumination intensity profile of an illuminator that forms part of a projection lithography system. Radiation from the illuminator is projected towards an illumination profile mask having a plurality of apertures such that each aperture passes a distinct portion of the radiation. The intensity of each of the distinct portions of radiation is detected and assembled to form the illumination intensity profile.

Device and method for determining an illumination intensity profile of an illuminator for a lithography system

The invention is a method of manufacturing a semiconductor device and such semiconductor device. The semiconductor device includes an integrated circuit pattern including a horizontal line, a vertical line and a space therebetween, the space including a precise width dimension. The method includes the steps of: forming a photosensitive layer to be patterned, patterning the photosensitive layer to form a pattern including a master horizontal line and a master vertical line without a space therebetween, transferring the pattern to at least one underlying layer using the patterned photosensitive layer, forming a second photosensitive layer over the patterned at least one underlying layer, patterning the second photosensitive layer to form a second pattern including a master space aligned to dissect a horizontal line and a vertical line formed in the at least one underlying layer, and transferring the second pattern to the at least one underlying layer to form a third pattern including a horizontal line and a vertical line with a space therebetween, the space including a precise width dimension.

Growing community of inventors

Sunnyvale, CA, United States of America

Christopher A Spence