Cypress Semiconductor Corporation

Christopher A Seams

Anantha R Sethuraman

Krishnaswamy Ramkumar

Mira Ben-Tzur

Thurman John Rodgers

William W C Koutny, Jr

Yonghong Yang

Clifford P Sandstrom

Prakash R Krishanan

A method for arranging a semiconductor wafer within a photolithography tool and methods for processing a semiconductor wafer employing such an arrangement process are provided. The arrangement process includes positioning a semiconductor wafer on a stage in a pre-alignment unit of a photolithography tool such that a crystal orientation marker of the wafer is located at a first radial position. Thereafter, the wafer is moved to an exposure unit of the photolithography tool. During one or both of such steps, the semiconductor wafer is rotated such that the crystal orientation marker is relocated to a second, distinct radial position prior to arranging the wafer upon a stage of the exposure unit. In particular, the semiconductor wafer is rotated greater than approximately 10&#xb0; and less than approximately 170&#xb0; relative to the first radial position. The arrangement process is performed for lithography processes conducted during fabrication of a semiconductor device.

Method for arranging and rotating a semiconductor wafer within a photolithography tool prior to exposing the wafer

In one embodiment, a metal level includes a plurality of metal lines. A low-k dielectric is deposited over the metal level such that an air gap forms at least between two metal lines. The relatively low dielectric constant of the low-k dielectric reduces capacitance on metal lines regardless of whether an air gap forms or not. The air gap in the low-k dielectric further reduces capacitance on metal lines. The reduced capacitance translates to lower RC delay and faster signal propagation speeds.

Low-k dielectric layer with air gaps

The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by forming a plurality of dummy features in a dielectric layer between a relatively wide interconnect and a series of relatively narrow interconnect. According to an embodiment, a plurality of laterally spaced dummy trenches are first etched in the dielectric layer between a relatively wide trench and a series of relatively narrow trenches. The dummy trenches, the wide trench, and the narrow trenches are filled with a conductive material, e.g., a metal. The conductive material is deposited to a level spaced above the upper surface of the dielectric layer. The surface of the conductive material is then polished to a level substantially coplanar with that of the upper surface of the dielectric layer. Advantageously, the polish rate of the conductive material above the dummy trenches and the wide and narrow trenches is substantially uniform. In this manner, dummy conductors spaced apart by dielectric protrusions are formed exclusively in the dummy trenches, and interconnect are formed exclusively in the narrow and wide trenches. The topological surface of the resulting interconnect level is substantially void of surface disparity.

Planarized semiconductor interconnect topography and method for polishing a metal layer to form interconnect

The present invention advantageously provides a substantially planarized semiconductor topography and method for making the same by selectively etching a dielectric layer to form a plurality of posts surrounded by trenches. The trenches are filled with a conductive material, such as a metal, deposited to a level spaced above the upper surfaces of the dielectric layer and the posts. The surface of the conductive material is then polished to a level substantially coplanar with the upper surfaces of the dielectric layer and the posts. Advantageously, the polish rate of the conductive material above the trenches is substantially uniform. In this manner, the topological surface of the resulting interconnect level is substantially void of surface disparity.

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Pleasanton, CA, United States of America

Christopher A Seams