Synopsys, Inc.

Christopher A Kopetzky

Shivakumar Shankar Chonnad

Thomas Warren Savage

Manickam E Kandaswamy

Maulin Bhatt

An HDL-based ASIC design is translated from a first RTL description to a second RTL description. The first RTL description describes the HDL-based ASIC design through a first set of modules arranged in a hierarchical manner. Translation includes: creating a reference gate-level netlist by synthesizing the HDL-based ASIC design described using the first RTL description; creating a second set of modules by translating the first RTL description of the first set of modules to the second RTL description module by module; and creating a combined RTL and gate-level design by integrating at least one module from the second set of modules within the reference gate-level netlist. Each module translated into the second RTL description may be also checked for compilation warning or error messages. If any warning or error messages are generated, the offending module(s) is modified to eliminate the warning or error messages. In addition, each module described using the first RTL description may be functionally compared with each module described using second RTL description. If any functional discrepancy exists between corresponding first and second RTL modules, the offending module described using the second RTL description is modified to rectify the functional discrepancy. Top-level simulation may be also performed on all of the modules that are described using the second RTL description.

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Mountain View, CA, United States of America

Christopher A Kopetzky