Apple Inc.

Christopher A Burns

Justin A Hensley

Ali Rabbani Rankouhi

Terence M Potter

Liang-Kai Wang

Jonathan M Redshaw

Luca O Iuliano

Robert D Kenney

Yoong Chert Foo

Andrew M Havlir

Richard Warren Schreyer

Yu P Sun

Andrew S Pomianowski

Anthony P DeLaurier

Xiao-Long Wu

Nicolas Xavier Pena

Casper R W Van Benthem

Techniques are disclosed relating to ray tracing and motion blur in graphics processors. In some embodiments, ray intersection accelerator circuitry is configured to perform traversal operations for an acceleration data structure (ADS) that includes hierarchical bounding volumes, where the ADS includes a first node that specifies: first coordinates of a bounding volume at a first motion blur time and second coordinates of the bounding volume at a second motion blur time. The Ray accelerator may determine a ray time interval representation indicating upper and lower bounds that represent error bounds for a quantized ray time value of a ray. Interpolation circuitry may operate on the first coordinates, the second coordinates, and the ray time interval representation to generate interpolated coordinates for the bounding volume. Box test circuitry may determine whether the ray intersected the bounding volume based on the interpolated coordinates and coordinates of the ray.

Hardware acceleration for motion blur with ray tracing

Techniques are disclosed relating to conversion operations in the context of integer and floating-point processor operations. In some embodiments, floating-point pipeline circuitry is configured to execute a single instruction to convert an N-bit integer value to an M-bit floating-point result. To execute the instruction, source modifier circuitry may generate an intermediate M-bit representation based on the N-bit integer value. Fused multiply-add circuitry may perform a fused multiply-add operation to generate the M-bit floating-point result, where the fused multiply-add operation operates on: the intermediate M-bit representation, a quantization scale factor value indicated by the instruction, and a zero-point value indicated by the instruction. In some embodiments that support down-conversion, the floating-point pipeline circuitry is also configured to execute a single instruction to convert an M-bit floating-point value to an N-bit integer result value.

Hardware support for conversion between integer and floating-point data

Techniques are disclosed relating to scheduling instructions for floating-point execution units with different capabilities. In some embodiments, a first pipeline is configured to execute a first type of floating-point operation on operands having up to a first precision and a second pipeline is configured to execute the first type of floating-point operation on operands having up to a second, greater precision. In some embodiments, round circuitry is configured to round results from an output precision of the second pipeline to an output precision of the first pipeline. Scheduling circuitry may select operations for issuance for a given cycle from multiple ready threads. This may include to prioritize a determined highest-precision operation of the first type from ready operations and assign the determined operation to a lowest-precision pipeline, of the multiple pipelines, that is configured to perform the first type of operation according to the operand precision of the determined operation.

Superscalar execution using pipelines that support different precisions

Techniques are disclosed relating to intersection tests for ray tracing in graphics processors. In some embodiments, test circuitry is configured to perform an intersection test based on traversal of an acceleration data structure that includes hierarchically-arranged bounding volumes for a graphics scene, where the test operates on: reduced-precision representations of rays that are quantized versions of initial representations of the rays and reduced-representatives of primitives that are quantized versions of initial representations of the primitives. The test may generate a first result for a first ray and a first primitive that indicates that a line coincident with the first ray definitively intersects the first primitive. The graphics processor may record an intersection for the first ray with the first primitive, based on the first result, without performing an intersection test for the first ray using the initial representation of the first ray and the first primitive.

Quantized ray intersection testing with definitive hit detection

Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline. In some embodiments, the routing circuitry may support a shift and fill instruction that facilitates storage of an arbitrary portion of a graphics frame in one or more registers.

SIMD operand permutation with selection from among multiple registers

Techniques are disclosed relating to testing whether a ray intersects a graphics primitive, e.g., for ray tracing. In some embodiments, intersection circuitry performs a reduced-precision conservative intersection test and shader circuitry performs an original-precision intersection test if the intersection circuitry indicates a hit. The intersection circuitry may quantize the ray (and may quantize the primitive or may receive a quantized representation of the primitive) and generates a potential error value based on propagation of quantization error for the primitive and ray. The intersection circuitry then determines an intersection result for the reduced-precision test based on the quantized primitive data and the potential error. In various embodiments, disclosed techniques may improve performance or reduce power consumption by reducing the number of original-precision intersection tests that do not result in hits.

Primitive testing for ray intersection at multiple precisions

Disclosed techniques relate to forming single-instruction multiple-data (SIMD) groups during ray intersection traversal. In particular, ray intersection circuitry may include dedicated circuitry configured to traverse an acceleration data structure, but may dynamically form a SIMD group to transform ray coordinates when traversing from one level of the data structure to another. This may allow shader processors to execute the SIMD group to perform the transformation. Disclosed techniques may facilitate instancing of graphics models within the acceleration data structure.

SIMD group formation techniques during ray intersection traversal

Techniques are disclosed relating to intersection tests for ray tracing in graphics processors. In some embodiments, test circuitry is configured to perform intersection tests that operate on reduced-precision representations of rays that were generated by quantizing initial representations of the rays and reduced-precision representations of primitives that were generated by quantizing initial representations of the primitives. Some reduced-precision tests (e.g., for any-hit rays) may generate a definitive hit according to the initial representations. In this situation, graphics processing circuitry may record an intersection with the reduced-precision representation of the primitive for the ray based on the first result, without performing an intersection test for the first ray using the initial representation of the ray and the primitive. Disclosed techniques may advantageously reduce power consumption, improve performance, or both.

Techniques are disclosed relating to primitive intersection testing for ray tracing in graphics processors. In some embodiments, a graphics processor includes ray intersection circuitry configured to perform an intersection test, which includes to: quantize a first representation of the primitive to generate a reduced-precision interval representation of the primitive, quantize a first representation of the ray to generate a reduced-precision interval representation of the ray, and determine, using interval arithmetic, an initial intersection result based on coordinates of the interval representation of the primitive and coordinates of the interval representation of the ray. The initial intersection result may be a conservative result such that a miss indicated by the initial intersection result is guaranteed not to be a hit for the first representation of the primitive and first representation of the ray. Disclosed techniques may improve performance, reduce power consumption, or both, relative to traditional techniques.

Ray intersection testing with quantization and interval representations

Techniques are disclosed relating to ray intersection in the context of motion blur. In some embodiments, a graphics processor includes time-oblivious ray intersect circuitry configured to receive coordinates for a ray and traverse a bounding volume hierarchy (BVH) data structure based on the coordinates to determine whether the ray intersects with one or more bounding regions of a graphics space. In some embodiments, in response to reaching a temporal branch element of the BVH data structure, the ray intersect circuitry initiates a shader program that determines a sub-tree of the BVH data structure for further traversal by the ray intersection circuitry, where the sub-tree corresponds to a portion of a motion-blur interval in which the ray falls. This may provide accurate ray tracing for motion blur while reducing area and power consumption of intersect circuitry, relative to time-aware implementations.

Temporal split techniques for motion blur and ray intersection

Disclosed techniques relate to primitive testing associated with ray intersection processing for ray tracing. In some embodiments, shader circuitry executes a first SIMD group that includes a ray intersect instruction for a set of rays. Ray intersect circuitry traverses, in response to the ray intersect instruction, multiple nodes in a spatially organized acceleration data structure (ADS). In response to reaching a node of the ADS that indicates one or more primitives, the apparatus forms a second SIMD group that executes one or more instructions to determine whether a set of rays that have reached the node intersect the one or more primitives. The shader circuitry may execute the first SIMD group to shade one or more primitives that are indicated as intersected based on results of execution of the second SIMD group. Thus, disclosed techniques may use both dedicated ray intersect circuitry and dynamically formed SIMD groups executed by shader processors to detect ray intersection.

SIMD group formation techniques for primitive testing associated with ray intersect traversal

Disclosed techniques relate to grouping rays during traversal of a spatially-organized acceleration data structure (e.g., a bounding volume hierarchy) for ray intersection processing. The grouping may provide temporal locality for accesses to bounding region data. In some embodiments, ray intersect circuitry is configured to group rays based on the node of the data structure that they target next. The ray intersect circuitry may select one or more groups of rays for issuance each clock cycle, e.g., to bounding region test circuitry.

Grouping techniques for ray intersection traversal

Disclosed techniques relate to ray intersection processing for ray tracing. In some embodiments, ray intersection circuitry traverses a spatially organized acceleration data structure and includes bounding region circuitry configured to test, in parallel, whether a ray intersects multiple different bounding regions indicated by a node of the data structure. Shader circuitry may execute a ray intersect instruction to invoke traversal by the ray intersect circuitry and the traversal may generate intersection results. The shader circuitry may shade intersected primitives based on the intersection results. Disclosed techniques that share processing between intersection circuitry and shader processors may improve performance, reduce power consumption, or both, relative to traditional techniques.

Ray intersect circuitry with parallel ray testing

Disclosed techniques relate to an acceleration data structure for ray intersection with a many-to-many mapping between bounding regions and primitives. In some embodiments, one or more graphics processors access data for multiple graphics primitives in a graphics scene and generate a spatially organized data structure. Some nodes of the data structure indicate graphics primitives and some nodes indicate coordinates of bounding regions in the graphics scene. In some embodiments, the spatially organized data structure includes a node with a bounding region for which multiple primitives are indicated as children and also includes a primitive for which multiple bounding regions are indicated as parents. Disclosed techniques may generate bounding regions that closely fit primitives, which may reduce primitive testing for ray tracing. This in turn may increase performance or reduce power consumption relative to traditional techniques.

Growing community of inventors

Austin, TX, United States of America

Christopher A Burns