International Business Machines Corporation

Christophe Robert Tretz

Wei Hwang

George Diedrich Gristede

Shikhar Kwatra

Ching-Te Kent Chuang

Salvatore Nicholas Storino

Jerry C Kao

Mario M Pelella

Paul J Landsberg

Chung-Tao Li

Embodiments for intelligent temporary contact sharing between user equipment (UE) by a processor. A temporary exchange of contact data may be provided between a first UE and a second UE via a wireless communication network according to one or more policies, user preferences, historical data, a defined physical or virtual proximity between the first UE and the second UE, or a combination thereof. The contact data may be automatically deleted between the first UE and the second UE according to the one or more policies, the user preferences, the historical data, the defined physical or virtual proximity between the first UE and the second UE, or a combination thereof.

Intelligent temporary contact sharing between user equipment

A method utilizes an array of functionally interchangeable dynamic logic cells to implement an application specific logic function in an integrated circuit design. Each functionally interchangeable dynamic logic cell is comprised of a dynamic logic circuit configured to generate an output as a function of a plurality of inputs, and an output latch that is configured to latch the output generated by the logic circuit. The array of functionally interchangeable dynamic logic cells are used to implement an application specific logic function within a specific logic design by routing a plurality of conductors between inputs and outputs of at least a subset of the functionally interchangeable dynamic logic cells.

Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells

A circuit arrangement, integrated circuit device, apparatus, program product, and method utilize an array of functionally interchangeable dynamic logic cells to implement an application specific logic function in an integrated circuit design. Each functionally interchangeable dynamic logic cell is comprised of a dynamic logic circuit configured to generate an output as a function of a plurality of inputs, and an output latch that is configured to latch the output generated by the logic circuit. The array of functionally interchangeable dynamic logic cells are used to implement an application specific logic function within a specific logic design by routing a plurality of conductors between inputs and outputs of at least a subset of the functionally interchangeable dynamic logic cells.

A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the NAND. A sleep signal provides a second input to the NAND. An output of the NAND provides an input to the inverter logic that inverts the NAND output and provides a complementary output. The NAND logic includes a series connected first sleep transistor receiving the sleep input. The first sleep transistor is turned OFF during the sleep mode. A second sleep transistor is connected between a voltage supply rail and the NAND output. The second sleep transistor is turned ON during the sleep mode to force high the NAND output and force low complementary output.

Method and apparatus for implementing subthreshold leakage reduction in LSDL

A method for reducing a hysteresis effect in silicon-on-insulator CMOS circuits includes the steps of providing a circuit having CMOS objects, defining a beta ratio; resizing the CMOS objects based on the beta ratio, determining if the objects are a minimum size based on predetermined size criteria, if the objects are larger than the minimum size, defining a scaling factor based on a performance level of the object and resizing the object based on the scaling factor such that delay variations of the resized circuit are substantially constant. Also, a computer program product is provided for reducing the hysteresis effect.

Method and system for reducing hysteresis effect in SOI CMOS circuits

A method for automatically tuning object sizes in an integrated circuit includes the steps of providing a circuit having objects disposed therein, inputting equations associated with the objects to provide a relationship between a size of the object and timing information of signals transmitted between the objects, extracting transition times of the signals transmitted between objects by simulating the circuit in operation by evaluating the equations and adjusting the sizes of the objects in the circuit according to the timing information and the transition times until user defined criteria are achieved for the circuit. Systems are also provided to carry out the method.

Method and system for tuning of components for integrated circuits

A method of automatically selecting object size in an integrated circuit includes the steps of providing a circuit topology having objects disposed therein, inputting equations associated with the objects to provide sizing adjustment for the objects, assigning parameter values in the equations based on physical constraints of the circuit for one or more objects, selecting one or more objects to be sized, evaluating cones of influence for the objects selected to identify influenced objects influenced by a change in the selected object and computing for each selected object and influenced objects, a size in accordance with the associated equation until a user defined criteria is achieved for the circuit. A system for performing the method of the present invention is also described.

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San Jose, CA, United States of America

Christophe Robert Tretz