International Business Machines Corporation

Christophe Piveteau

Abu Sebastian

Manuel Le Gallo-Bourdeau

Evangelos Stavros Eleftheriou

Stefan Woerner

Irem Boybat Kara

Vinay Manikrao Joshi

David Sutter

Jay Michael Gambetta

Nikolas Ioannou

Paul Kristan Temme

Sergey Bravyi

Riduan Khaddam-Aljameh

Nandakumar Sasidharan Rajalekshmi

Igor Krawczuk

Techniques facilitating error mitigation for quantum computing devices. In one example, a system can comprise a process that executes computer executable components stored in memory. The computer executable components comprise: an approximation component; a budget component; and an optimization component. The approximation component can generate an approximate decomposition of a quantum gate. The budget component can set a budget value (C) for a C-factor that is a metric for increase in variance of quasi-probability sampling. The optimization component can determine an optimal decomposition for the quantum gate as a function of C.

Quantum error mitigation using hardware-friendly probabilistic error correction

The present disclosure relates to an electronic system for computing items of an outer product matrix, for each item of at least part of the items of the matrix. The system is configured to receive a pair of real numbers of two vectors, the pair corresponding to the item. The system is further configured to compute a stochastic representation of the real numbers resulting in two sets of bits, the set of bits comprising a subset of bits representing the real number and a sign bit indicative of the sign of the real number. The system is further configured to perform a sequence of digital operations using the two sets of bits to provide a representation of the item.

Electronic system for computing items of an outer product matrix

Methods and apparatus are provided for training an artificial neural network, having a succession of neuron layers with interposed synaptic layers each storing a respective set of weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for at least one of the synaptic layers, providing a plurality Pof arrays of memristive devices, each array storing the set of weights of that synaptic layer Sin respective memristive devices, and, in a signal propagation operation, supplying respective subsets of the signals to be weighted by the synaptic layer Sin parallel to the Parrays. The method also includes, in a weight-update calculation operation, calculating updates to respective weights stored in each of the Parrays in dependence on signals propagated by the neuron layers.

Training of artificial neural networks

Methods are provided for training weights of an artificial neural network to be implemented by inference computing apparatus in which the trained weights are stored as programmed conductance states of respective predetermined memristive devices. Such a method includes deriving for the memristive devices a probability distribution indicating distribution of conductance errors for the devices in the programmed conductance states. The method further comprises, in a digital computing apparatus: training the weights via an iterative training process in which the weights are repeatedly updated in response to processing by the network of training data which is propagated over the network via the weights; and applying noise dependent on said probability distribution to weights used in the iterative training process.

Techniques that combine quantum error correction and quantum error mitigation are used to simulate a fault-tolerant T-gate with low sampling overhead using the quasiprobability decomposition method. In some embodiments, the T-gate can be simulated using two logical bits and a magic state preparation that mitigates the need for magic state distillation and consequently has a low sampling overhead. Alternatively, the T-gate can be simulated based on code deformation performed on the surface code. Noise is removed from the T-gate using quasiprobability decomposition based on a learned logical error rate.

Fault-tolerant T-gates via quasiprobability decomposition

The present disclosure relates to a method for executing a computation task composed of at least one set of operations where subsets of pipelineable operations of the set of operations are determined in accordance with a pipelining scheme. A single routine may be created for enabling execution of the determined subsets of operations by a hardware accelerator. The routine has, as arguments, a value indicative of input data and values of configuration parameters of the computation task, where a call of the routine causes a scheduling of the subsets of operations on the hardware accelerator in accordance with the values of the configuration parameters. Upon receiving input data of the computation task, the routine may be called to cause the hardware accelerator to perform by the computation task in accordance with the scheduling.

Method for interfacing with hardware accelerators

A system can include a memristive crossbar array, which can include row lines and column lines intersecting the row lines. Resistive memory elements can be coupled between the row lines and the column lines at the junctions formed by the row and column lines. The resistive memory elements represent the values of the matrix. The system can further include an analogue circuit. The system can be configured to perform an exponentiation of the values of the vector in accordance with a first exponent. The crossbar array can be configured to apply the resulting values of the vector to the resistive elements thereby generating currents. The analogue circuit can be configured to perform an exponentiation of the generated currents in accordance with a second exponent.

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Zurich, Switzerland

Christophe Piveteau