S.o.i.tec Silicon on Insulator Technologies

S.o.i. Tec Silicon on Insulator Technologies, S.a.

Soitec

Commissariat a L'energie Atomique

Other

National University of Singapore

Peregrine Semiconductor Corporation

Commissariat À L'energie Atomique (Cea)

Altatech Semiconductor

Applied Materials, Inc.

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Unity Semiconductor Corporation

S.o.i. Tec Silicon

Christophe Maleville

Walter Schwarzenbach

Eric Neyret

Bich-Yen Nguyen

Hubert Moriceau

Bernard Aspar

Michel Bruel

Nadia Ben Mohamed

Corinne Maunand Tussot

Fabrice Letertre

Mariam G Sadaka

Olivier Rayssac

Sébastien Kerdiles

Thierry Barge

Ludovic Ecarnot

Kiyoshi Mitani

Masatake Nakano

Susumu Kuwabara

Naoto Tate

Vivien Renauld

Oleg Kononchuk

Sinan Goktepeli

Didier Landru

Carlos Mazure

Ionut Radu

Alain Duvallet

Nicolas Daval

Daniel Delprat

Frédéric Allibert

Christophe Morales

Patrick Reynaud

Philippe Gastaldo

Eric Guiot

Thibaut Maurice

Isabelle Bertrand

Frédéric Metral

Alain Soubie

Anthony Mark Miscione

Damien Massy

Hugo Biard

Jean-Luc Delcarri

Benjamin Scarfogliere

Cécile Delattre

François Berger

Cécile Moulin

Sophie Moritz

Nadia Ben Mohammed

Patrice Belin

Emmanuel Aréne

Fredéric Metral

Andr&eacute;-Jacques Auberton-Herve

Gong Xiao

Chen Sun

Haiwen Xu

Aaron Thean

Christophe Girard

Oleg Kononchuck

Youngpil Kim

Chee Hoe Wong

Tussot Corinne Maunand

André-Jacques Auberton-Herve

A semiconductor structure, including: a base substrate; an insulating layer on the base substrate, the insulating layer having a thickness between about 5 nm and about 100 nm; and an active layer comprising at least two pluralities of different volumes of semiconductor material comprising silicon, germanium, and/or silicon germanium, the active layer disposed over the insulating layer, the at least two pluralities of different volumes of semiconductor material comprising: a first plurality of volumes of semiconductor material having a tensile strain of at least about 0.6%; and a second plurality of volumes of semiconductor material having a compressive strain of at least about −0.6%. Also described is a method of preparing a semiconductor structure and a segmented strained silicon-on-insulator device.

Device architectures with tensile and compressive strained substrates

A method of producing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate of silicon carbide comprises: a) a step of provision of an initial substrate of monocrystalline silicon carbide, b) a step of epitaxial growth of a donor layer of monocrystalline silicon carbide on the initial substrate, to form a donor substrate, c) a step of ion implantation of light species into the donor layer, to form a buried brittle plane delimiting the thin layer, d) a step of formation of a carrier substrate of silicon carbide on the free surface of the donor layer, comprising a deposition at a temperature of between 400° C. and 1100° C., e) a step of separation along the buried brittle plane, to form the composite structure and the remainder of the donor substrate, and f) a step of chemical-mechanical treatment(s) of the composite structure.

Method for producing a composite structure comprising a thin layer of monocrystalline sic on a carrier substrate of polycrystalline SiC

A method of manufacturing a substrate for a front-facing image sensor, comprises:—providing a donor substrate comprising a semiconductor layer to be transferred,—providing a semiconductor carrier substrate,—bonding the donor substrate to the carrier substrate, an electrically insulating layer being at the bonding interface,—transferring the semiconductor layer to the carrier substrate,—implanting gaseous ions in the carrier substrate via the transferred semiconductor layer and the electrically insulating layer, and—after the implantation, epitaxially growing an additional semiconductor layer on the transferred semiconductor layer.

Method for manufacturing a substrate for a front-facing image sensor

A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor layer over a high-resistivity substrate, such that the dielectric layer is arranged between the high-resistivity substrate and the semiconductor layer; b) forming a hard mask or resist over the semiconductor layer, wherein the hard mask or resist has at least one opening at a predetermined position; c) forming at least one doped region in the high-resistivity substrate by ion implantation of an impurity element through the at least one opening of the hard mask or resist, the semiconductor layer and the dielectric layer; d) removing the hard mask or resist; and e) forming a radiofrequency (RF) circuit in and/or on the semiconductor layer at least partially overlapping the at least one doped region in the high-resistivity substrate.

Method for manufacturing a high-resistivity semiconductor-on-insulator substrate including an RF circuit overlapping a doped region in the substrate

The invention relates to a structure for radiofrequency applications comprising: a monocrystalline substrate, a polycrystalline silicon layer directly on the monocrystalline substrate, and an active layer on the polycrystalline silicon layer intended to receive radiofrequency components. At least a first portion of the polycrystalline silicon layer extending from an interface of the polycrystalline silicon layer with the monocrystalline substrate layer includes carbon and/or nitrogen atoms located at the grain boundaries of the polycrystalline silicon layer at a concentration of between 2% and 20%. A process for manufacturing such a structure includes, during deposition of at least a first portion of such a polycrystalline silicon layer located at the interface with the monocrystalline substrate, depositing carbon and/or atoms in the at least a first portion.

Structure for radiofrequency applications and process for manufacturing such a structure

Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures

Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers

A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.

Process for the transfer of a thin film comprising an inclusion creation step

A method for fabricating a substrate of the semiconductor on insulator type by forming an epitaxial layer of semiconducting material on a donor substrate having oxygen precipitates with a density of less than 10/cmor a mean size of less than 500 nm, forming an oxide layer on either a donor or receiver substrate, implanting atomic species in the donor substrate to form a weakened zone in the epitaxial layer, bonding the donor and receiver substrates together, with the oxide layer present at the bonding interface, fracturing the donor substrate in the weakened zone to transfer a layer of the donor substrate to the receiver substrate with the transferred layer including the epitaxial layer, and recycling the remainder of the donor substrate to form a receiver substrate for fabrication of a second semiconductor on insulator type substrate.

Method for fabricating a semiconductor on insulator type substrate

A method for fabricating a semiconductor on insulator substrate by providing a first semiconductor substrate with a first impurity density of a first impurity type, subjecting the first semiconductor substrate to a first thermal treatment to thereby reduce the first impurity density in a modified layer adjacent a surface of the first semiconductor substrate being treated, transferring at least partially the modified layer with the reduced first impurity density onto a second substrate, to thereby obtain a modified second substrate, and providing a further layer on a transferred layer of the modified second substrate with the further layer having a second impurity density of a second impurity type that is different than the first impurity type of the transferred modified layer. By doing so, a contamination by dopants of the second impurity type of a fabrication line using semiconductor material with dopants of the first impurity type, can be prevented.

Method for fabricating a semiconductor substrate

A method for minimizing or avoiding contamination of a receiving handle wafer during transfer of a thin layer from a donor wafer. This method includes providing a donor wafer and a receiving handle wafer, each having a first surface prepared for bonding and a second surface, with the donor wafer providing a layer of material to be transferred to the receiving handle wafer. Next, at least one of the first surfaces is treated to provide increased bonding energy when the first surfaces are bonded together; the surfaces are then bonded together to form an intermediate multilayer structure; and a portion of the donor wafer is removed to transfer the thin layer to the receiving handle wafer and form the semiconductor structure. This method avoids or minimizes contamination of the second surface of the receiving handle wafer by treating only the first surface of the donor wafer prior to bonding by exposure to a plasma, and by conducting any thermal treatments after plasma activation at a temperature of 300&#xb0; C. to 500&#xb0; C. in order to avoid diffusion of impurities into the transfer layer.

Transfer method with a treatment of a surface to be bonded

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La Terrasse, France

Christophe Maleville