Stmicroelectronics Gmbh

Stmicroelectronics S.a.

Arm Limited

Sgs-thomson Microelectronics S.a.

Christophe Frey

Richard P Fournel

Cyrille Dray

Sébastien Barasinski

Jean Lasseuguette

Mark A Lysinger

Frederic Lalanne

St&eacute;phane Hanriat

Franck Genevaux

Andrew John Sowden

David Turgis

Jean-Christophe Lafont

The power control circuitry comprises a series of power switching circuits, each power switching circuit being associated with one of the circuit portions and being provided with an enable signal and responsive to its enable signal being set to connect the voltage source to the at least one voltage line of the associated circuit portion. Further, at least one enable qualifying circuit is provided, each such enable qualifying circuit being associated with one of the power switching circuits and being arranged to generate an output signal used to determine the enable signal provided to a later power switching circuit in the series. Each enable qualifying circuit sets its output signal when both the enable signal provided to the associated power switching circuit is set and the at least one voltage line of the circuit portion associated with that power switching circuit has reached a predetermined voltage level.

Power control circuitry and method

A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.

Magnetic random access memory array having bit/word lines for shared write select and read operations

A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. These magnetic tunnel junctions are connected to each other in a series resistive circuit. The connected first and second magnetic tunnel junctions are connected to a bit line through an access transistor. A write bit line and a write data line are associated with each of the first and second magnetic tunnel junctions. By application of appropriate currents to these lines, the magnetic vector orientation with each of the first and second magnetic tunnel junctions can be controlled so as to store information within the element in any one of at least three logic states.

Multi-bit magnetic random access memory element

A memory cell (), includes a flip-flop () that has additional read/write terminals; a 1-bit write line (wb); a first transistor (T) switching between the 1-bit write line and the terminal, its gate being connected to a word selection line (W); a 0-bit write line (wb); a second transistor (T) switching between the 0-bit write line and the terminal, its gate being connected to a word selection line (W); a bit read line (b); and read transistors (T, T), with one of their gates being connected to a read/write terminal and the other being connected to a word selection line.

Random access memory cell of reduced size and complexity

A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.

Memory architecture with segmented writing lines

A random access memory array includes random access memory elements arranged in a rows and columns. Each row is divided into a plurality of row groups of elements and each column is divided into a plurality of column groups of elements. The elements in each row group share a common local write digit line and the elements in each column group share a common local write bit line. The array further includes at least one global write digit line coupled to the common local write digit lines of plural row groups, and at least one global write bit line coupled to the common local write bit lines of plural column groups.

Magnetic random access memory array with global write lines

A random access memory array includes first random access memory elements arranged in a plurality of rows and columns for storing data words at a multiple memory locations. The memory array further includes second random access memory elements arranged in at least one additional column. Each second random access memory element is associated with a memory location to store a flag value indicative of whether the data word stored at that memory location is a true or complement version. The individual memory elements may comprise magnetic random access memory elements. Alternatively, the individual memory elements may comprise flash memory cells.

Random access memory array with parity bit structure

A magnetic random access memory element is made from a first magnetic tunnel junction and a second magnetic tunnel junction. A latching circuit includes a false node that is connected to the first magnetic tunnel junction and a true node that is connected to the second magnetic tunnel junction. A pair of complementary bit lines are provided in association with the element. A first access transistor inter-connects a false one of the bit lines to the false node of the latching circuit, while a second access transistor inter-connects a true one of the bit lines to the true node of the latching circuit. The memory element accordingly has an SRAM four transistor (4T) two load (2R) architecture wherein the resistances associated with the two magnetic tunnel junctions provide the two load resistances.

Magnetic random access memory element

An integrated circuit includes a memory, and the memory includes a memory plane arranged in rows and columns, and a plurality of read amplifiers connected to the columns of the memory plane. A reference path includes first and second reference columns, and a reference memory cell is connected between the first and second reference columns. A reference row is connected to the reference memory cell for selection thereof so that the first reference column conducts a discharge current and the second reference column conducts a leakage current. A control circuit is connected between the first and second reference columns and the read amplifiers. The control circuit provides an activation signal to the read amplifiers when an absolute value of a difference between voltages on the first and second reference columns exceeds a threshold.

Process for controlling the read amplifiers of a memory and corresponding memory integrated circuit

A Content Addressable Memory (CAM) cell is disclosed having an physical implementation of transistors for improving the semiconductor substrate area utilization of the CAM cell and the CAM array. The CAM cell comprises a first and second memory circuit and a compare circuit. The compare circuit of six transistors formed over two active regions. The local interconnect between the compare circuit and the first memory circuit formed of a polysilicon region. The local interconnect between the compare circuit and the second memory circuit formed of polysilicon and conductive regions.

CAM cell having compare circuit formed over two active regions

A memory cell is formed with a buffer circuit. The output of the buffer circuit is linked to the input to form a logic latch. A write-access transistor is disposed between a first node linked to a bit line and the input of the buffer circuit. A control gate of the write-access transistor is linked to a second node linked to a write word line, and a read-access transistor is disposed between the first node linked to the bit line and a third node linked to a read word line. A control gate of the read-access transistor is linked to the output of the buffer circuit.

Memory cells incorporating a buffer circuit and memory comprising such a memory cell

The present invention relates to a method of functional testing of a logic circuit and to an integrated circuit for implementing the method. The method includes providing at least one test pattern and the storage of this test pattern in a first test register, this providing step being synchronized by an external clock signal; serially providing of this test pattern to an input of the internal logic circuit, this providing step being synchronized by a test clock signal generated from an internal clock signal; storing, in a second test register connected to the output of the internal logic circuit, at least one resulting pattern generated by the internal logic circuit when the test pattern is provided thereto, this storing being synchronized by the test clock signal; and providing to the outside, by series shifting, of the resulting pattern, this providing step being synchronized by the external clock signal.

Functional testing method and circuit including means for implementing said method

An integrated circuit includes an array of memory cells that are selected by rows and read by columns. The columns are first precharged by an internal signal to then read the memory cells. The read is responsive to an edge of a clock signal and the read is of an unknown delay. A multiplexer output provides the internal signal. The multiplexer includes a plurality of inputs electrically connected to delay lines of different delay sizes that receive the edge of the clock signal. A multiplexer control circuit selects a delay line to provide the internal signal as soon as possible after the unknown delay.

Growing community of inventors

Austin, TX, United States of America

Christophe Frey