Arm Limited

Christophe Denis Lucien Frey

Nicolaas Klarinus Johannes Van Winkelhoff

Vincent Philippe Schuppe

Yannick Marc Nevers

Sebastien Nicolas Ricavy

Mikael Brun

Denis René André Dufourt

A memory device and method of operating such a device are provided. The memory device has a plurality of sub-arrays arranged to form at least one sub-array column having a first end and a second end, with each sub-array comprising a plurality of memory cells arranged in a plurality of memory cell rows and at least one memory cell column. Sub-array access circuitry is associated with each sub-array, for detecting read data from a selected memory cell column of the associated sub-array during a read operation, and global access circuitry then interfaces with the first end of the sub-array column. Each sub-array access circuitry comprises propagation circuitry for producing an output read data value, the propagation circuitry having a first input for receiving the read data detected from the associated sub-array during a read operation and a second input for receiving an output read data value produced by a linked sub-array access circuitry associated with a sub-array nearer the second end of the sub-array column. The propagation circuitry receives a control signal for identifying which of its first or second inputs should be used to produce the output read data value. As a result, an output read data value produced by any sub-array access circuitry is propagated to the global access circuitry via any linked sub-array access circuitry in the sub-array column between that sub-array access circuitry and the global access circuitry. This provides a particularly simple technique for propagating the read data value to the global access circuitry, which has both predictable timing, and consumes low power.

Memory device with propagation circuitry in each sub-array and method thereof

A memory is disclosed that comprises: an input for receiving an input signal and an output for outputting data; a plurality of data storage cells for storing individual units of data; said plurality of data storage cells being arranged in an array; a plurality of said arrays; each of said arrays comprising detecting circuitry for detecting and outputting stored data in response to a control signal received at said detecting circuitry; delay circuitry for providing a delay to said control signal sent to said detecting circuitry of at least some of said plurality of arrays, said delay provided to said control signal being longer for at least one array located closer to an input and output of said memory than it is to at least one array located further from an input and output of said memory.

Accessing data within a memory formed of memory banks

A read only memory cell for storing a multiple bit value is disclosed. The read only memory cell comprises: at least three output lines, each of the at least three output lines representing a different multiple bit value; a switching device connected between a single one of the three output lines and a voltage source. The switching device provides an electrical connection between the voltage source and the single one of the three output lines in response to a switching signal, a voltage of the connected output line switching value in response to connection to the predetermined voltage and the multiple bit value represented by the output line is thereby selected. There is also an output device provided for outputting the selected multiple bit value.

Read only memory cell for storing a multiple bit value

A data processor includes a memory device having an array of memory cells for storing data values. Test circuitry executes one or more test patterns to detect any memory cells which may malfunction. Each test pattern causes a sequence of access requests to be issued to the memory device where the timing of the sequence is controlled by a test mode clock signal. Dummy read control circuitry is responsive at least to each write access request to generate an internal clock signal which has an increased frequency with respect to the test mode clock signal. The dummy read control circuitry performs, using the internal clock signal, a write operation to at least one memory cell based on a memory address specified by the write access request, followed by a dummy read operation to the same memory cell, serving to stress the memory cell with respect to cell stability.

Data processing apparatus and method for testing stability of memory cells in a memory device

A memory device and method of operation are provided. The memory device comprises a plurality of memory cells arranged in at least one column, during a write operation a data value being written to an addressed memory cell within a selected column from said at least one column. A supply voltage line is associated with each column, the supply voltage line being connectable to a first voltage source to provide a supply voltage at a first voltage level to the associated column. Threshold circuitry is connected to a second voltage source having a second voltage level, the threshold circuitry having a threshold voltage. Control circuitry is used during the write operation to disconnect the supply voltage line for the selected column from the first voltage source, and to connect the threshold circuitry to the supply voltage line for the selected column. As a result, the supply voltage to the addressed memory cell transitions to an intermediate voltage level determined by the threshold voltage of the threshold circuitry, thereby de-stabilizing the addressed memory cell and assisting in the write operation. The technique of the present invention provides a particularly simple and power efficient technique for implementing a write assist mechanism.

Growing community of inventors

Meylan, France

Christophe Denis Lucien Frey