Qualcomm Incorporated

Christophe Avoinne

Rakesh Kumar Gupta

Bohuslav Rychlik

Laurent Rene Moll

Kun Xu

Vaishnav Srinivas

Philippe Boucard

Jean-Jacques Lecler

Thomas Zeng

Subbarao Palacharla

Alain Artieri

Jason Edward Podaima

Shyamkumar Thoziyoor

Samir Vijay Ginde

Kedar Bhole

Xavier Loic Leloup

Mahalingam Nagarajan

Michael David Jager

Luc Montperrus

Manokanthan Somasundaram

Syed Minhaj Hassan

Sparsh Singhai

Gopi Tummala

Carlo Spitale

Luigi Vinci

Jaya Subramaniam Ganasan

Manav Shah

Sanjay Jaisingh Arya

Siddharth Kamdar

Interconnections for modular die designs are disclosed. In one aspect, a die that is a chiplet is designed and tested for suitability. After approval of the chiplet design, multiple dies or chiplets may be coupled together within a multi-die package to form a package having desired computing capabilities. After assembly, each chiplet is provided a unique identifier, such as by setting a fuse. Based on the unique identifier, each chiplet is made aware of how interfaces to other chiplets are configured so that signals may be routed appropriately. Using modular chiplets in this fashion reduces testing requirements and non-recurring expenses while increasing flexibility for design options.

Interconnections for modular die designs

A method for providing low latency frequency switching includes operating a first processing component on a first die and operating a second processing component on a second die with the same first clock signal having a first frequency. A request to switch the first frequency to a second, new frequency is received and a second clock signal having the second, new frequency is produced. Data flow between the first die and second die may be stopped. And then the second clock signal is transmitted to a dual phased locked loop architecture on a die interface. A PCLK signal is created from the combined first and second clock signals and an NCLK signal is created from the second clock signal. Next, the PCLK signal is divided and aligned with the NCLK signal. Once the PCLK signal is aligned with the NCLK signal, data flow is resumed between the two dies.

System for providing a low latency and fast switched cascaded dual phased lock loop (PLL) architecture for die-to-die / system-on-chip (SoC) interfaces

Data caching may include storing data associated with DRAM transaction requests in data storage structures organized in a manner corresponding to the DRAM bank, bank group and rank organization. Data may be selected for transfer to the DRAM by selecting among the data storage structures.

Dram-aware caching

Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.

Coherent interconnect power reduction using hardware controlled split snoop directories

Aspects include computing devices, apparatus, and methods for accelerating distributive virtual memory (DVM) message processing in a computing device. DVM message interceptors may be positioned in various locations within a DVM network of a computing device so that DVM messages may be intercepted before reaching certain DVM destinations. A DVM message interceptor may receive a broadcast DVM message from first DVM source. The DVM message interceptor may determine whether a preemptive DVM message response should be returned to the DVM source on behalf of the DVM destination. When certain criteria are met, the DVM message interceptor may generate a preemptive DVM message response to the broadcast DVM message, and send the preemptive DVM message response to the DVM source.

Interconnect distributed virtual memory (DVM) message preemptive responding

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Campbell, CA, United States of America

Christophe Avoinne