Advanced Micro Devices Corporation

Globalfoundries Inc.

Christoph Schwan

Kai Frohberg

Manfred Horstmann

Andreas Kurz

Thorsten E Kammler

Joe Bloomquist

Sven Beyer

Srikanteswara Dakshina-Murthy

Peter Javorka

Matthias Lehr

Matthias Schaller

Roman Boschke

Frank Wirbeleit

Gunter Grasshoff

Markus Forsberg

Karla Romero

John Morgan

Jan Hoentschel

Andy C Wei

Karsten Wieczorek

Uwe Griebenow

Rolf Stephan

Thomas Feudel

Martin Gerhardt

Carsten Hartig

Kay Hellig

Kerstin Ruttloff

Volker Grimm

Katja Huy

Sven Mueller

Jeffrey C Haines

Markus Forseberg

In SOI devices, the PN junction of circuit elements, such as substrate diodes, is formed in the substrate material on the basis of the buried insulating material that provides increased etch resistivity during wet chemical cleaning and etch processes. Consequently, undue exposure of the PN junction formed in the vicinity of the sidewalls of the buried insulating material may be avoided, which may cause reliability concerns in conventional SOI devices comprising a silicon dioxide material as the buried insulating layer.

SOI device with a buried insulating material having increased etch resistivity

A semiconductor-based electronic fuse may be provided in a sophisticated semiconductor device having a bulk configuration by appropriately embedding the electronic fuse into a semiconductor material of reduced heat conductivity. For example, a silicon/germanium fuse region may be provided in the silicon base material. Consequently, sophisticated gate electrode structures may be formed on the basis of replacement gate approaches on bulk devices substantially without affecting the electronic characteristics of the electronic fuses.

Methods of forming efuse devices

In sophisticated semiconductor devices, electronic fuses may be provided on the basis of a replacement gate approach by using the aluminum material as an efficient metal for inducing electromigration in the electronic fuses. The electronic fuse may be formed on an isolation structure, thereby providing an efficient thermal decoupling of the electronic fuse from the semiconductor material and the substrate material, thereby enabling the provision of efficient electronic fuses in a bulk configuration, while avoiding incorporation of fuses into the metallization system.

Electronic fuse structure formed using a metal gate electrode material stack configuration

In integrated circuits, resistors may be formed on the basis of a silicon/germanium material, thereby providing a reduced specific resistance which may allow reduced dimensions of the resistor elements. Furthermore, a reduced dopant concentration may be used which may allow an increased process window for adjusting resistance values while also reducing overall cycle times.

Semiconductor device comprising a silicon/germanium resistor

By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.

Semiconductor device comprising isolation trenches inducing different types of strain

By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided, thereby enhancing performance of P-channel transistors. The position and size of the strain-inducing region may be determined on the basis of an implantation mask and respective implantation parameters, thereby providing a high degree of compatibility with conventional techniques, since the strain-inducing region may be incorporated at an early manufacturing stage, directly to respective 'large area' contact elements.

Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region

By performing a planarization process, for instance based on a planarization layer, prior to forming a resist mask for selectively removing a portion of a stressed contact etch stop layer, the strain-inducing mechanism of a subsequently deposited further contact etch stop layer may be significantly improved.

Method for patterning contact etch stop layers by using a planarization process

A technique is provided that enables the formation of metal silicide individually for N-channel transistors and P-channel transistors, while at the same time a strain-inducing mechanism is also provided individually for each transistor type. In this way, a cobalt silicide having a reduced distance to the channel region of an NMOS transistor may be provided, while a P-channel transistor may receive a highly conductive nickel silicide, without unduly affecting or compromising the characteristics of the N-channel transistor.

Technique for forming contact insulation layers and silicide regions with different characteristics

A vertical or three-dimensional non-planar configuration for a decoupling capacitor is provided, which significantly reduces the required die area for capacitors of high charge carrier storage capacity. The non-planar configuration of the decoupling capacitors also provides enhanced pattern uniformity during the highly critical gate patterning process.

Semiconductor device including a vertical decoupling capacitor

By recessing the isolation structure of a transistor prior to silicidation, the series resistance may be reduced due to the increased amount of metal silicide formed in the vicinity of the isolation structure. By recessing the isolation structure prior to the formation of the gate electrode, an increased degree of poly wrap around may be obtained, thereby increasing the effective channel width.

Method of increasing transistor drive current by recessing an isolation trench

By increasing the transistor topography after forming a first layer of highly stressed dielectric material, additional stressed material may be added, thereby efficiently increasing the entire layer thickness of the stressed dielectric material. The corresponding increase of device topography may be accomplished on the basis of respective placeholder structures or dummy gates, wherein well-established gate patterning processes may be used or wherein nano-imprint techniques may be employed. Hence, in some illustrative embodiments, a significant increase of strain may be obtained on the basis of well-established process techniques.

Field effect transistor having a stressed dielectric layer based on an enhanced device topography

A method of forming a field effect transistor comprises providing a substrate comprising, at least on a surface thereof, a first semiconductor material. A recess is formed in the substrate. The recess is filled with a second semiconductor material. The second semiconductor material has a different lattice constant than the first semiconductor material. A gate electrode is formed over the recess filled with the second semiconductor material.

Field effect transistor comprising a stressed channel region and method of forming the same

Method of making a semiconductor device comprising isolation trenches inducing different types of strain

The present invention makes it possible to precisely deposit a material adjacent a feature on a substrate. A layer of the material is deposited on the substrate. The layer is planarized and exposed to an etchant. The etchant is adapted to selectively remove the material. The exposing of the layer to the etchant is stopped prior to a complete removal of the layer.

Method of depositing a layer of a material on a substrate

By heat treating a silicon dioxide liner prior to patterning a silicon nitride spacer layer, the etch selectivity of the silicon dioxide with respect to the silicon nitride is increased, thereby reducing or eliminating the problem of pitting through the silicon dioxide layer. This allows further scaling of the devices, wherein an extremely thin silicon dioxide liner is required to obtain an accurate lateral patterning of the dopant profile in the drain and source regions.

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Gebhardshain, Germany

Christoph Schwan