Infineon Technologies Ag

Infineon Technologies Austria Ag

Lantiq Deutschland Gmbh

Siemens Aktiengesellschaft

Lantiq Beteiligungs Gmbh & Co. Kg

Christoph Sandner

Andreas Wiesbauer

Giuseppe Li Puma

Stefano Marsili

Christian Grewing

Stefan Van Waasen

Martin Friedrich

Kay Winterberg

Guenter Hofer

Gerhard Maderbacher

Matteo Agostinelli

Yossi Erlich

Klaus Hoermaier

Andreas Berger

Manfred Punzenberger

Nicola Da Dalt

Herwig Wappis

Cheow Guan Lim

Josef Höglauer

Andrea Bevilacqua

Clemens Roessler

Roman Riederer

Stephan Auer

Mark Schauer

Johannes Thielmann

Staffan Ek

Federico Pietro Pavan

Michael Sieberer

A device for controlling trapped ions includes an ion trap, a plurality of field electrodes configured to control ions in the ion trap, and a controller chip. The controller chip includes at least one delta-sigma digital to analog converter (DS-DAC) module including a DS-DAC circuit configured to receive a digital data stream, convert the digital data stream to analog control voltages, and supply the analog control voltages to the field electrodes.

Device for controlling trapped ions and including a delta/sigma dac module

In accordance with an embodiment, a method includes receiving, by at least one of a plurality of battery monitoring circuits a frequency synchronization signal and measurement frequency information from a host controller, wherein the at least one of the plurality of battery monitoring circuits is connected to at least one of a plurality of battery blocks; generating, by the at least one of the plurality of battery monitoring circuits, a periodic signal based on a clock signal having a clock frequency, the measurement frequency information, and the frequency synchronization signal; obtaining, by the at least one of the plurality of battery monitoring circuits, at least one measurement value of the at least one of the plurality of battery blocks using the periodic signal; and transmitting, by the at least one of the plurality of battery monitoring circuits, the at least one measurement value to the host controller.

Method of monitoring a battery, monitoring system and monitoring circuit

A method and a temperature detection circuit are disclosed. An example of the method includes driving an alternating current with a first frequency into a battery and detecting an imaginary part of a battery impedance at the first frequency; driving an alternating current with a second frequency different from the first frequency into the battery and detecting an imaginary part of the battery impedance at the second frequency; and calculating an intercept frequency at which the imaginary part equals a predefined value at least based on the imaginary part obtained at the first frequency and the imaginary part obtained at the second frequency.

Battery temperature detection

A circuit is described that includes a rectifier configured to rectify a DC output from an AC input, a sensing unit configured to detect a voltage level of the DC output, and a control unit configured to control the rectifier based on the voltage level of the DC output. The control unit is configured to control the rectifier output by at least controlling the rectifier to rectify the DC output from the AC input if the voltage level of the DC output does not indicate an overvoltage condition at the circuit. In addition, the control unit is configured to control the rectifier based on the voltage level of the DC output by at least controlling the rectifier to shunt current from the AC input if the voltage level of the DC output does indicate the overvoltage condition.

Overvoltage protection for a synchronous power rectifier

Representative implementations of devices and techniques determine the timing of switches associated with a dc-dc converter. The determination is based on a body diode conduction of at least one of the switches, which is detected and used to determine a switching delay.

Dead-time optimization of DC-DC converters

Methods, devices, and integrated circuits are disclosed for providing a buck converter charger in a multiphase buck converter topology comprising at least a first phase, a second phase, and an alternative charging switch, wherein the first phase includes a first high-side switch and a first low-side switch and the second phase includes a second high-side switch and a second low-side switch. The methods, devices, and integrated circuits may control at least one phase to operate as a boost converter, control at least one phase to operate as buck converter, and close the alternative charging switch in the multiphase buck converter topology to connect an alternative charging source to a system voltage output, the alternative charging switch coupled to the first phase between the first high-side switch and the first low-side switch.

Reconfigurable multiphase power stage for switched mode chargers

A power converter is described that includes components arranged within a first die and a second die of a single package. The first die includes one or more first switches coupled to a switching node of a power stage. The second die includes one or more second switches coupled to the switching node of the power stage, a feedback control unit configured to detect a current level at the one or more second switches of the power stage, and a controller unit configured to control the one or more first switches and the one or more second switches of the power stage based at least in part on the current level detected by the feedback control unit.

Switched-mode power converter with split partitioning

Amplifier for an ultra-wideband (UWB) signal receiver having a signal input () for receiving an ultra-wideband signal which is sent by a transmitter () and which is transmitted in a sequence of transmission channels (K.sub.i) (which each have a particular frequency bandwidth) which has been agreed between the transmitter () and the receiver (); a transistor () whose control connection is connected to the signal input (); a resonant circuit () which is connected to the transistor () and whose resonant frequency can be set for the purpose of selecting the transmission channel (K.sub.i) in line with the agreed sequence of transmission channels; and having a signal output () for outputting the amplified ultra-wideband signal, the signal output being tapped off between the transistor () and the resonant circuit.

Ultra-wideband signal amplifier

A fast frequency-hopping transceiver comprises a RF-unit arranged on a first chip, a base-band unit on a second chip, a bidirectional operable data and control interface arranged between said first and said second chip having at least one data line for data communication, at least one control line for controlling the data communication and at least one clock line for providing a clock signal, memory means implemented within said RF-unit containing all the required chip settings which are specific to a certain frequency of received and/or transmitted data being part of the intended hopping sequence. The transceiver also includes control means for programming said memory means during an initialization phase during a set-up of a communication link of said data communication.

Fast frequency-hopping transceiver and method

Amplifier for an ultra-wideband (UWB) signal receiver having a signal input () for receiving an ultra-wideband signal which is sent by a transmitter () and which is transmitted in a sequence of transmission channels (K) (which each have a particular frequency bandwidth) which has been agreed between the transmitter () and the receiver (); a transistor () whose control connection is connected to the signal input (); a resonant circuit () which is connected to the transistor () and whose resonant frequency can be set for the purpose of selecting the transmission channel (K) in line with the agreed sequence of transmission channels; and having a signal output () for outputting the amplified ultra-wideband signal, the signal output being tapped off between the transistor () and the resonant circuit.

A method and an arrangement for processing a received signal which comprises phase-shift modulated or amplitude-quadrature modulated part-signals which are transmitted in a plurality of different frequency bands, wherein the received signal is processed in a plurality of stages in succession, by multiplying all the input signals to each of the stages by two mutually orthogonal signals in each case to form two intermediate signals in each case, wherein the intermediate signals from one stage in each case act as the input signals to whichever is the succeeding stage in the particular case and the received signal acts as the input signal to the first stage, and wherein an in-phase and/or an quadrature component of the individual part-signals in the different frequency bands are determined from the intermediate signals from the last stage. Parallel, simultaneous reception of a plurality of frequency bands can be implemented relatively easily in this way.

Demodulating a signal having multiple frequency bands

Frequency pattern generator () for generating frequency pulses, said generator having a first local oscillator unit (-) for generating a first radio frequency carrier frequency signal (LO), at least one second local oscillator unit (--N,) for generating at least one second radio frequency carrier frequency signal (LO), a switching device () for passing on one of the radio frequency carrier frequency signals (LO, LO) or a zero signal (DC) in a manner dependent on a control signal (CTR), and a mixing stage () for mixing the signal (LO) that has been passed on by the switching device () with a mixing frequency signal (LF) to form a pulsed output signal (RFOUT), the pulsed output signal (RFOUT) having frequency pulses at a respective frequency (f, . . . f) and length (Tp) in a manner dependent on the control signal (CTR).

Low-loss frequency pattern generator

System and method for generating multiple local oscillator signals comprising a first-stage phase-locked loop (PLL) having an input to receive a first reference signal input and having an output to transmit a second reference signal, wherein the second reference signal is an integer or fractional multiple of the first reference signal; and a plurality of second-stage PLLs, each second-stage PLL having an input coupled to the output of the first-stage PLL and receiving the second reference signal, and each second-stage PLL having an output for transmitting a local oscillator signal, wherein each of the local oscillator signals is an integer multiple of the second reference signal.

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Villach, Austria

Christoph Sandner