Qimonda Ag

Infineon Technologies Ag

Advanced Mask Technology Center Gmbh + Co. Kg

Christoph Noelscher

Rolf Weis

Dirk Manger

Roderick Koehle

Dominique Savignac

Dietmar Temmler

Stephan Wege

Rainer Pforr

Molela Moukara

Steffen Meyer

Nicolo Morgana

Burkhard Ludwig

Carla Byloos

Sebastian Mosler

Haiko Rolff

Bernd Kuechler

Ralf Neubauer

Yi-Ming Chiu

Yuan-Hsun Wu

A lithographic mask comprises a first layer including grooves, a second layer including regions, sections and a groove-like structure that encloses the sections. The first and second layers are formed so as to reduce electrical potential differences within the second layer. A method of forming a lithographic mask includes forming first and second layers to dispose the second layer over the first layer, patterning the second layer to comprise sections, a region, and a groove-like structure enclosing the sections, and forming grooves in the first layer at portions not covered by the second layer. The first and second layers are formed to reduce potential differences within the second layers during the step of forming the grooves in the first layer.

Lithographic mask and method of forming a lithographic mask

A method of double patterning is disclosed. The method includes forming a first photosensitive layer; exposing the first photosensitive layer using a first reticle; developing the first photosensitive layer thereby forming a first image pattern including first elements; forming a second photosensitive layer; exposing the second photosensitive layer using the first reticle; and developing the second photosensitive layer thereby forming a second image pattern.

Method of double patterning, method of processing a plurality of semiconductor wafers and semiconductor device

The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step.

Method of fabricating a semiconductor device

One possible embodiment is a method of manufacturing a structure on or in a substrate with the following steps

Methods for generating sublithographic structures

The invention is concerned with a method for manufacturing a local wiring in a semiconductor device, comprising the manufacturing of at least two electrically conducting structures essentially in the same horizontal level in a layered stack on a substrate, the at least two electrically conducting structures being separated by a gap filled with at least one dielectric material, the gap being electrically bridged by conductive material, to form at least one contact element electrically connecting the at least two electrically conducting structures, whereby at least one contact element is produced in a single lithographic step.

Method for manufacturing a structure in a semiconductor device and a structure in a semiconductor device

A method of fabricating an integrated circuit, including the steps of forming a first mask layer in the form of a hard mask layer including a plurality of first openings and a second mask layer with at least one second opening which at least partially overlaps with one of the first openings, wherein the at least one second opening is generated lithographically; and at least two neighboring first openings are distanced from each other with a center to center pitch smaller than the resolution limit of the lithography used for generating the second opening.

Method of fabricating an integrated circuit

In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions.

Method for forming a structure on a substrate and device

A semiconductor device with a substrate includes a structure. The structure has a first part and a second part. At least one section of the edge of the first part of the structure is at an essential constant distance measured parallel to the substrate to a first section of an edge of a second structure. At least one section of the edge of the second part of the structure is lined with an edge of a second section of the same second section. The first section of the edge of the second structure and a second section of the edge of the second structure merge at least at one point, whereby the angle between the tangents of the edges of the first and second section of the second structure is less than 90&#xb0;. The structure and the second structure are distanced by a spacer structure.

Semiconductor device, method for manufacturing a semiconductor device and mask for manufacturing a semiconductor device

The invention relates to a method for optimizing a mask layout pattern comprising at least one structural feature. First a desired layout pattern is provided. Based on the desired layout pattern, an optimized reference diffraction coefficient is provided. After selecting an initial mask geometry having polygon-shaped structures, initial diffraction coefficients are calculated. A difference based on the reference diffraction coefficient and initial diffraction coefficients is used to optimize the initial geometry in order to provide a mask layout pattern.

Method for optimizing a photolithographic mask

A photolithography mask is based on a combination of a half-tone phase mask and an alternating phase mask such that, when the radiation passes through some of the openings, a phase difference is in each case produced between adjacent openings, and the surroundings of the openings are partially transparent and shift the phase of the radiation. Consequently, the advantages of alternating phase masks and half-tone phase masks can be realized on one mask and, accordingly, significantly enlarged process windows for the actual lithography process result with the photolithography mask according to the invention. In particular, these advantages can be obtained with only one absorber material, and the size of non-imaging auxiliary structures is approximately as large as the smallest main structure. In addition, the invention provides methods for fabricating the photolithography masks according to the invention.

Growing community of inventors

Nuremberg, Germany

Christoph Noelscher