Infineon Technologies Ag

Siemens Aktiengesellschaft

Christoph Kutter

Christoph Ludwig

Georg Tempel

Klaus-Dieter Morhard

Elard Stein Von Kamienski

Kai Huckels

Peter Wawer

Georg Georgakos

Jakob Kriz

Olaf Heitzsch

Konrad Wolf

Reinhold Rennekamp

Andreas Liebelt

Oliver Springmann

Mayk R&ouml;hrich

A semiconductor structurecomprises a plurality of first track conductors, a plurality of second track conductors, which are insulated with respect to the first track conductorsand form a grid together with these first track conductors, and a plurality of third track conductorsparallel above the first track conductors, which third track conductorspartly cover the second track conductorsand are insulated with respect thereto, in which semiconductor structure, between in each case two adjacent second track conductors, there is located an electrical contactbetween each first track conductorand the corresponding third track conductorwhich lies above it.

Method for generating an electrical contact with buried track conductors

Semiconductor structure having buried track conductors, and method for generating an electrical contact with buried track conductors

A nonvolatile NOR semiconductor memory device and a method for programming the memory device are described. The memory device has a multiplicity of one-transistor memory cells disposed in a matrix form being driven both via word lines and via bit lines. In this case, each one-transistor memory cell has both a source line and a drain line, as a result of which selective driving of the respective drain and source regions is obtained. In this way, a leakage current in the semiconductor memory device can be optimally reduced with minimal space requirement.

Nonvolatile nor semiconductor memory device and method for programming the memory device

A method for producing a non-volatile semiconductor memory cell with a separate tunnel window cell includes the step of forming a tunnel zone in a late implantation step by performing a tunnel implantation with the aid of a tunnel window cell as a mask. The resulting memory cell has a small area requirement and a high number of program/clear cycles.

Method for fabricating a non-volatile semiconductor memory cell with a separate tunnel window

A method for fabricating a memory cell array, in particular an EPROM or EEPROM memory cell array, includes burying insulation zones on a silicon substrate in accordance with an STI (Shallow Trench Isolation) technique, forming word lines on the insulation zones, covering the word lines with a hard mask and side wall oxides and CVD depositing an oxide or nitride laterally onto the hard mask and onto the side wall oxides to define a spacer. Spacer channels are etched into the insulation zones between adjoining word lines. An SAS (Self Aligned Source) resist mask is applied to mask each two adjacent coated word lines on mutually facing sections, including the spacer channel located between these word lines, while each two adjacent masked word lines of masked word line pairs remain unmasked on mutually facing sections. The SAS resist mask is exposed. Those regions of the insulation zones which are not covered by the SAS perforated mask are anisotropic etched, with a bottom of uncovered spacer channels being lowered down at least to a surface of the uncovered silicon substrate. The SAS perforated mask is removed to uncover a resultant structure.

Method for fabricating a memory cell array

The read only memory has a plurality of conductor track planes one above the other. The conductor tracks in adjacent planes are oriented such that they intersect in intersecting regions. In these intersecting regions, either a VIA tunnel contact is provided, which represents a logic '1' or no VIA tunnel contact is provided, so that this intersecting region represents a logic '0'. In this way, over the same surface area, a plurality of memory cells can be produced one above the other. The read only memory is produced with a defined sequence of process steps and it is operated by selectively applying predetermined voltages across the various conductor tracks.

Read only memory

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Dresden, Germany

Christoph Kutter