Infineon Technologies Ag

Qimonda Ag

Infineon Technologies Flash Gmbh & Co. Kg

Infineon Technology Ag

Christoph Kleint

Joachim Deppe

Christoph Ludwig

Jens-Uwe Sachse

Josef Willer

Nicolas Nagel

Ricardo Pablo Mikalo

Dominik Olligs

David Pritchard

Mathias Krause

Günther Wein

Roman Knoefler

Clemens Fitz

Matthias Markert

Ulrike Bewersdorff-Sarlette

Steffen Meyer

Mark Isler

Jan-Malte Schley

Eike Ruttkowski

Hocine Boubekeur

Erwin Schroer

Ralf Richter

Torsten Müller

Patrick Haibach

A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures.

Integrated circuit including structures arranged at different densities and method of forming the same

An integrated circuit and a method of forming an integrated circuit. One embodiment includes a conductive line formed above a surface of a carrier. A slope of the sidewalls of the conductive line in a direction perpendicular to the surface of the carrier reveals a discontinuity and a width of the conductive line in an upper portion thereof is larger than the corresponding width in the lower portion.

Integrated circuit and method of forming an integrated circuit

A memory device having an array portion including memory cells, and a peripheral portion including conductive lines is disclosed. In one embodiment, portions of the conductive lines adjoin a surface of a semiconductor carrier.

Memory device, a non-volatile semiconductor memory device and a method of forming a memory device

A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.

Buried bitline with reduced resistance

An interconnection structure includes two staggered contact rows of evenly spaced contacts. Each contact row extends along a first direction. The interconnection structure further includes conductive lines extending along a second direction that intersects the first direction. The interconnection structure further includes intermediate contacts, where each intermediate contact is in contact with one of the contacts and one of the conductive lines.

Interconnection structure and method of manufacturing the same

A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.

Method of forming contacts using auxiliary structures

A non-volatile semiconductor memory () comprising a semiconductor substrate () and a plurality of memory cells () and methods for manufacturing such a memory is provided. Each memory cell () comprises a charge-trapping element (), a gate stack (), nitride spacers () and electrically insulating elements (). The charge-trapping element () is arranged on the semiconductor substrate () and comprises a nitride layer () sandwiched between a bottom oxide layer () and a top oxide layer (), the charge-trapping element () having two lateral sidewalls () opposed to one another. The gate stack () is arranged on top of the charge-trapping element (), the gate stack having two lateral sidewalls () opposing one another. The electrically insulating elements () are disposed at opposing sidewalls () of the charge-trapping element () and cover the sidewalls () of the charge-trapping element (). The nitride spacers () cover the electrically insulating elements () and are arranged on opposing sidewalls () of the gate stack () and on the electrically insulating elements ().

Semiconductor memory

In the method, trenches () are etched and, in between, bit lines () are in each case arranged on doped source drain/regions (). Dopant is introduced into the bottoms of the trenches () in order to form doped regions (), in order to electrically modify the channel regions. Storage layers are applied and gate electrodes () are arranged at the trench walls. The semiconductor material at the bottoms of the trenches is etched away between the word lines () to an extent such that the doped regions () are removed there to such a large extent that a crosstalk between adjacent memory cells along the trenches is reduced.

Method for fabricating an NROM memory cell arrangement

A trench () is fabricated in a silicon body (). The walls () of the trench are provided with a nitrogen implantation (). An oxide layer between the source/drain regions () and a word line applied on the top side grows to a greater thickness than a lower oxide layer of an ONO storage layer fabricated as gate dielectric at the trench wall. Instead of the nitrogen implantation into the trench walls, it is possible to fabricate a metal silicide layer on the top sides of the source/drain regions in order to accelerate the oxide growth there.

SONOS memory cells and arrays and method of forming the same

In a memory cell, in a trench, a layer sequence comprising a first oxide layer, a nitride layer provided on the first oxide layer, and a second oxide layer, facing the gate electrode, and provided at the lateral trench walls, while the nitride layer is absent in a curved region of the trench bottom. In an alternative configuration, in each case at least one step is formed at the lateral walls of the trench, preferably below the source region or the drain region, respectively.

Memory cell

An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer () and before the etching of the trench, an implantation is introduced for the purpose of defining the position of the junctions, or, after the implantation of the n-type well () for the source/drain regions, the bit line layer () is patterned using an etching stop layer () arranged on the semiconductor body ().

Method for fabricating NROM memory cells with trench transistors

An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source/drain junctions of transistors of the addressing circuitry.

Charge-trapping memory device

In the method, trenches are etched and, in between, bit lines () are in each case arranged on doped source/drain regions (). Storage layers () are applied and gate electrodes () are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes (), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer () is reached, and afterward a polysilicon layer (), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.

Method for fabricating an NROM memory cell array

Electrically conductive material is introduced into interspaces between the word lines () and is partially removed using a mask () in such a way that residual portions () of the conductive material in each case fill a section of the relevant interspace and produce an electrical contact with source/drain regions (). With further portions of the conductive material, it is possible to form alignment marks for the fabrication process.

Method for fabricating a semiconductor memory having charge trapping memory cells and semiconductor substrate

A method for manufacturing a semiconductor device includes forming a storage layer over a semiconductor body. The storage layer includes a first boundary layer, an intermediate storage layer and a second boundary layer. The storage layer is patterned so that at least some of the storage layer is removed from over a first portion of the semiconductor body and some of the storage layer is removed from over a second portion of the semiconductor body. The first portion of the semiconductor body is doped and the second portion of the semiconductor body is etched.

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Dresden, Germany

Christoph Kleint