International Business Machines Corporation

Christoph Jaeschke

Bodo Hoppe

Johannes Koesters

Yee Ja

Robert Benjamin Gass

Cedric Lichtenau

Thomas Pflueger

Jochen Preiss

Tobias Gemmeke

Jens Kuenzer

A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.

Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip

An apparatus and computer program product for driving values to 'don't care' (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the apparatus and computer program product, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the apparatus and computer program product may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.

Driving values to DC adjusted/untimed nets to identify timing problems

The present invention relates to a system for verifying the proper operation of a digital logic circuit and program product therefore. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of:

System for performing verification of logic circuits

A method for driving values to 'don't care' (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the system and method, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the system and method may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.

Method for driving values to DC adjusted/untimed nets to identify timing problems

The present invention relates to a method for verifying the proper operation of a digital logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of:

Method for performing verification of logic circuits

The present invention relates to the field of computer hardware locic circuits, and in particular to a method for verifying the proper operation of a digital logic circuit, and in particular to symbolic simulation of a gate-level netlist corresponding to said hardware logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of:

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Tuebingen, Germany

Christoph Jaeschke