International Business Machines Corporation

Christoph Hermann Hagleitner

Jan Van Lunteren

Giora Biran

Timothy Hume Heil

Silvio Dragone

Raphael C Polig

Alessandro Curioni

Kubilay Atasu

Michel Despont

Konstantinos Bekas

Heiner Giefers

Russell Dean Hoover

Christoph M Angerer

Daniel Grogg

Yu Pu

Stefano Sergio Oggioni

Thomas Helmut Toifl

Francois Abel

Christian I Menolfi

Dionysios Diamantopoulos

Fabrice Jean Verplanken

Ute Drechsler

Mitra Purandare

Jonathan Bruno Rohrer

Burkhard Ringlein

Peter W J Staar

Costas Bekas

Charalampos Pozidis

Jean Louis Calvignac

Jason Raymond Baumgartner

Abu Sebastian

Martin L Schmatz

Uzi Shvadron

Frederick Ralph Reiss

Srikumar Venugopal

Michael Johnston

Adelmo Cristiano Innocenza Malossi

Florian Michael Scheidegger

Yves G Ineichen

Florian Dorfler

Jean L Cavignac

Florian Doerfler

Jagath Weerasinghe

Robert R McCune

An embodiment includes detecting a search request of a multi-dimensional search space by a system; responsive to detecting the search request, sampling representative parameters in the multi-dimensional search space based on a sampling threshold. The embodiment includes determining a parameter range of the representative parameters in the multi-dimensional search space. The embodiment also includes transforming a part of the multi-dimensional search space based on a statistical guarantee and the parameter range, where the part of the multi-dimensional search space is a refined space for a solution of the search request.

Refinement of large multi-dimensional search spaces

Field-programmable gate array and method to implement an artificial neural network. A trained model of the neural network is processed, in which weights are defined in a floating-point format, to quantize each set of weights to a respective reduced-precision format in dependence on effect of quantization on accuracy of the model. For each set of weights, a partitioning scheme is defined for a set of block memories of the apparatus such that a plurality k of those weights can be stored in each addressable location of the set of memories, wherein k differs for different sets of weights. The apparatus can be programmed to implement the neural network such that weights in each set are persistently stored in a set of block memories partitioned according to the partitioning scheme for that set of weights.

Artificial neural network implementation in field-programmable gate arrays

The present disclosure relates to a messaging method for a hardware acceleration system. The method includes determining exchange message types to be exchanged with a hardware accelerator in accordance with an application performed by the hardware acceleration system. The exchange message types indicate a number of variables, and a type of the variables, of the messages. The method also includes selecting schemas from a schema database. The message type schemas indicates a precision representation of variables of messages associated with the schema. The selected schemas correspond to the determined exchange message types. Further, the method includes configuring a serial interface of the hardware accelerator in accordance with the selected schemas, to enable a message exchange including the messages.

Messaging for a hardware acceleration system

The present disclosure relates to a hardware accelerator for executing a computation task composed of a set of operations. The hardware accelerator comprises a controller and a set of computation units. Each computation unit of the set of computation units is configured to receive input data of an operation of the set of operations and to perform the operation, wherein the input data is represented with a distinct bit length associated with each computation unit. The controller is configured to receive the input data represented with a certain bit length of the bit lengths and to select one of the set of computation units that can deliver a valid result and that is associated with a bit length smaller than or equal to the certain bit length.

Hardware accelerator for executing a computation task

Manufacturing a batch is provided which includes a plurality of items of an electronic device, the items including a plurality of corresponding main modules having a same functional structure substantially identical for the items. The method includes defining at least one security electric circuit, of an enclosure component for enclosing each item, adapted to protect the item from tampering, the security electric circuits having individual configurations substantially different among the items, for use in forming the security electric circuit with the corresponding configuration on each enclosure component. Additionally, the method includes determining one or more electric characteristics of each security electric circuit for use in configuring a monitoring circuit of the corresponding main module, the monitoring circuit being adapted to the corresponding security electric circuit for detecting the tampering, according to the electric characteristics of the corresponding security circuits.

Electronic devices with individual security circuits

According to some embodiments, a computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable gate array (FPGA) module comprising a k-stage pipeline is described. The method may include interleaving k-stage threads on the k-stage pipeline comprising a plurality of threads tto t, wherein a first result of thread tis ready one cycle after the first input of thread tis fed into the pipeline, and outputting a result matrix Y.

Sparse matrix multiplication using a single field programmable gate array module

A communication channel for reconfiguration of a device, such as an FPGA, is described in various embodiments. One embodiment includes a physical input/output circuit, a dynamic layer, and a static layer. The static layer is programmed into the reconfigurable device to contain a configuration layer and a network layer. The configuration layer is able to receive additional layers, such as a virtual network layer and a virtual security layer and program them into the reconfigurable device. The virtual network layer can provide communication protocols, such as TCP/IP, and the virtual security layer can provide security protocols, such as TLS and IPSec. Various distributed applications can be programmed into the reconfigurable device over the network and configured to use the virtual network layer and the virtual security layer.

Communication channel for reconfigurable devices

One or more embodiments may provide the capability to enumerate maximal cliques of graph data by constructing and traversing a search tree through a single sequential pass on an adjacency list. The adjacency list may be generated so as to enable the at least one maximal clique to be generated in one single sequential pass.

Graph data representation and pre-processing for efficient parallel search tree traversal

Embodiments of the present invention provide methods, computer program products, and systems for solving a linear equation system using a hardware-implemented extended solver, wherein a calculation precision is adapted in each iteration step of a solving process is provided. Embodiments of the present invention can be used to perform on-the-fly interpolations using the data associated with the highest resolution of the three-dimensional finite element voxel model to a lower resolution than the highest resolution as well as to perform solving computations of the solving process in the lower resolution.

Linear FE system solver with dynamic multi-grip precision

A non-deterministic finite state machine module for use in a regular expression matching system. The system includes a computational unit implementing a non-deterministic finite state machine representing a regular expression, wherein the computational unit is configured to: receive an input data stream, wherein an occurrence of the regular expression is determined, and an activation signal; process the input data stream with respect to the non-deterministic finite state machine depending on the activation signal; and provide at least one branch data output for initializing an additional non-deterministic finite state machine module if the processing of an element of the input data stream according to the non-deterministic finite state machine results in a branching of a processing thread.

Non-deterministic finite state machine module for use in a regular expression matching system

An iterative refinement apparatus configured to generate data defining a solution vector x for a linear system represented by Ax=b, where A is a predetermined matrix and b is a predetermined vector. An outer solver processes input data, defining the matrix A and vector b, in accordance with an outer loop of an iterative refinement method to generate said data defining the solution vector x. An inner solver processes data items in accordance with an inner loop of the iterative refinement method. The inner solver is configured to process said data items having variable bit-width and data format. A precision controller determines the bit-widths and data formats of the data items adaptively in dependence on the results of the processing steps of the iterative refinement method; the precision controller configured to control operation of the inner solver for processing said data items with the bit-widths and data formats.

Iterative refinement apparatus

A conjugate gradient solver apparatus is provided for generating data defining a solution vector x for a linear system represented by Ax=b where A is a predetermined matrix and b is a predetermined vector. The apparatus includes solver circuitry and a precision controller. The solver circuitry processes input data, defining said matrix A and vector b, in accordance with an iterative conjugate gradient method to generate said data defining the solution vector x. The solver circuitry is adapted to process data items, corresponding to vectors used in said conjugate gradient method, having a variable fixed-point data format. The precision controller determines the fixed-point data formats of respective said data items adaptively during progress of the conjugate gradient method in the solver circuitry.

Conjugate gradient solvers for linear systems

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Wallisellen, Switzerland

Christoph Hermann Hagleitner