Infineon Technologies Ag

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Infineon Technologies Austria Ag

Christoph Deml

Edvin Paparisto

Thomas Liebermann

Massimo Atti

Maciej Piotr Jankowski

Martin Bloch

Stephan Rogl

Michele Boraretto

A method and a corresponding circuit protect a power MOSFET from overload when switching the MOSFET off. The current through the MOSFET is compared to a reference signal depending on the time since switching the MOSFET on.

Method and circuit for protecting a MOSFET

An integrated circuit includes a transistor. During operation a current slew-rate is determined based on a duration the transistor has been conducting and a current flowing through the transistor. The transistor can then be controlled to switch to its non-conducting state using the slew-rate.

The invention relates to a method and a corresponding circuit for protecting a power MOSFET from thermal overload when switching the MOSFET off and on, wherein the MOSFET is switched on again after at least a determined off-period has passed.

An integrated circuit having a plurality of sectors is disclosed. One embodiment includes a sector driver for simultaneously driving word lines corresponding to a single sector, the sector driver being connected to each word line and comprising a programmable sector memory for storing the sectors and word lines corresponding to each sector.

Integrated circuit having a word line driver

A memory device, including a non-volatile memory device, a method for operating a memory device, and an apparatus for use with a memory device is disclosed. In one embodiment, the memory device includes at least one evaluation circuit for amplifying a signal resulting from the reading of a memory cell, and a device for precharging an output of the evaluation circuit to a predetermined voltage level.

Memory device, method for operating a memory device, and apparatus for use with a memory device

An integrated circuit having a memory arrangement is disclosed. In one embodiment, the memory arrangement includes a plurality of memory cells, a delete line for deleting the memory cells, and a read line for reading out the memory cells. There are either provided separate lines as delete line and as read line, or the same line serves both as delete line and as read line. The memory cell arrangement includes at least one delete memory sector and at least one read memory section. The number of memory cells of at least one delete memory sector does not concur with the number of memory cells of at least one read memory sector.

Integrated circuit having a memory arrangement

A method for erasing or programming a nonvolatile memory device comprising a memory cell, a sense amplifier, and a page memory, the method comprising the steps of: performing an erasure or programming operation in a manner dependent on the data stored in the page memory, reading out the content of the erased or programmed memory cells, modifying the content of the page memory in a manner dependent on the data read out, and performing a further erasure or programming operation in a manner dependent on the modified data, and the data read out from the erased or programmed memory cell being fed to the page memory, and the content of the page memory being modified in a manner solely dependent on these data and control signals controlling the temporal sequence.

Nonvolatile memory device for storing data and method for erasing or programming the same

Precharge arrangement for read access for integrated nonvolatile memories having at least one memory cell (), at least one source line (), at least one bit line (), at least one sense amplifier () and at least one precharge potential, the bit line () continuously having the precharge potential in a deselected state of the bit line (), and the source line () having a predetermined reference potential, in particular a ground potential (), in a selected state of the bit line ().

Precharge arrangement for read access for integrated nonvolatile memories

This invention provides a semiconductor memory device and a corresponding method of operation. The semiconductor memory device comprises a semiconductor substrate having a first conductivity; a plurality of gate structures for storing charge in a non-volatile manner regularly arranged in above the surface of the semiconductor substrate and electrically isolated therefrom; a plurality of wordlines, each of the gate structures being connected to one of the wordlines and a group of the gate structures being connected to a common wordline; and a plurality of active regions, each of the active regions being individually connectable to at least one of the gate structures.

Charge coupled EEPROM device and corresponding method of operation

In order to make memories more secure against interference occurring in operation, error correction devices are normally associated with them. If the memory contents of the storage location ( ) are accessed by evaluating the location current, the problem arises that the location current is both value-continuous and time-continuous. If leakage currents occur in the storage location ( ) that lead to an increased storage location current, then the current sensor amplifier ( ) can fall below these values only with a constantly increasing access time between the values 0 and 1. When leakage currents occur the current sensor amplifier ( ) for evaluating the location current may therefore switch over at arbitrary times. In order to be able to effect correctly a series-connected error correction in an error correction device ( ), in each case registers ( ) are interconnected between the current sensor amplifiers ( ) and the error correction device ( ) that intermediately store at a specific time (t ) the output signal of the current sensor amplifier ( ). Accordingly a switching over of the input signal of the error correction device ( ), which in certain circumstances could lead to an erroneous error correction, can be avoided during the error correction.

Circuit arrangement for the storage of digital data

A semiconductor memory device includes a semiconductor substrate having a first conductivity type and multiple parallel trenches extending in a first direction in the substrate. Each trench is filled with an isolation material and has an adjacent trench separated therefrom by a strip region. The device also includes multiple gate structures, for storing charge in a nonvolatile manner, arranged above the surface of the substrate and electrically isolated therefrom. The gate structures are arranged in parallel strips extending in a second direction that cross the strip regions. The device further includes multiple word lines, each of which is arranged on a corresponding gate structure from the multiple gate structures. The device also includes multiple active regions of a second conductivity type, each of which is arranged at one end of a corresponding strip region and each of which is electrically connectable to the gate structures of the corresponding strip region.

Semiconductor memory device

A charge pump configuration for matching a charge pump to prevailing conditions is described. The charge pump configuration according to the invention has a charge pump having a plurality of interconnected pump stages, with at least one respective pump capacitor, and a closed-loop control device. The closed-loop control device is configured such that it bridges or turns off at least one of the pump stages on the basis of the conditions that are to be taken into account. The pump stages needed by the charge pump configuration are optimally chosen for the present operating point on a basis of input and output voltages and currents, which allows the efficiency of the charge pump configuration to be set in optimum fashion.

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Munich, Germany

Christoph Deml