Infineon Technologies Ag

Christoph Bukethal

Thomas Nirschl

Jan Otterstedt

Danny Shum

Mayk Roehrich

John Power

Martin Stiftinger

In various embodiments, a level shifter and a method for operating the same are provided. The level shifter may include a low supply voltage terminal, a high supply voltage terminal, at least one input terminal, at least one output terminal, and a latch. The latch may configured to: store a predetermined logic state by setting a storage node to a voltage level in response to receiving a predetermined voltage level at the at least one input terminal; amend the voltage level at the storage node in response to receiving an amended voltage/s at the low supply voltage terminal and/or at the high supply voltage terminal; and output the predetermined logic state having the amended voltage level from the storage node to the at least one output.

Level shifter and method for operating the same

A method for manufacturing a memory cell in accordance with various embodiments may include: forming at least one charge storing memory cell structure over a substrate, the charge storing memory cell structure having a first sidewall and a second sidewall opposite the first sidewall; forming an electrically conductive layer over the substrate and the charge storing memory cell structure; patterning the electrically conductive layer to form a spacer at the first sidewall and a blocking structure at the second sidewall of the charge storing memory cell structure; implanting first dopant atoms to form a first doped region in the substrate proximate the spacer, wherein the first dopant atoms are blocked by the blocking structure; removing the blocking structure after implanting the first dopant atoms; implanting second dopant atoms to form a second doped region in the substrate proximate the second sidewall of the charge storing memory cell structure.

Method for manufacturing a memory cell, a method for manufacturing a memory cell arrangement, and a memory cell

A structure and method for increasing the operating speed and reducing the overall programming time of a memory array are provided herein. The method and structure reduce the maximum write current consumption, for writing a plurality of data bits to a NVM array, by writing the data bits sharing an activated word line at different times (e.g., activating bit lines associated with an activated word line at different times). The write operation of respective data bits, which individually utilize only a fraction of the overall write window of the bits, are interleaved so that the maximum write current of respective bits are offset in time from the maximum write current of another bit, allowing a larger number of data bits to be written without exceeding system specifications (e.g., maximum current) and reducing overall memory write time.

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Dresden, Germany

Christoph Bukethal