Imec Vzw

Imec

Katholieke Universiteit Leuven

Imec USA Nanoelectronics Design Center

Christoph Adelmann

Malgorzata Jurczak

Johan Swerts

Mauricio Manfrini

Xavier Rottenberg

Jorge Adrian Kittl

Silvia Armini

Cedric Huyghebaert

Bogdan Govoreanu

Roel Gronheid

Annelies Delabie

Ivan Pollentier

Sven Van Elshocht

Marina Yurievna Timmermans

Jae Uk Lee

Kim Vu Luong

Vicky Philipsen

Leqi Zhang

Gustaf Winroth

Emily Gallagher

Jorge Kittl

The present disclosure relates generally to Hf-comprising materials for use in, for example, the insulator of a RRAM device, and to methods for making such materials. In one aspect, the disclosure provides a method for the manufacture of a layer of material over a substrate, said method including wherein X is a halogen selected from Cl, Br, I and F and is preferably Cl.

Insulator material for use in RRAM

The disclosed technology generally relates to semiconductor devices, and more particularly to a device configured as one or both of a spin wave generator or a spin wave detector. In one aspect, the device includes a magnetostrictive film and a deformation film physically connected to the magnetorestrictive film. The device also includes an acoustic isolation surrounding the magnetostrictive film and the deformation film to form an acoustic resonator. When the device is configured as the spin wave generator, the deformation film is configured to undergo a change physical dimensions in response to an actuation, where the change in the physical dimensions of the deformation film induces a mechanical stress in the magnetostrictive film to cause a change in the magnetization of the magnetostrictive film. When the device is configured as the spin wave detector, the magnetostrictive film is configured to undergo to a change in physical dimensions in response to a change in magnetization, wherein the change in the physical dimensions of the magnetostrictive film induces a mechanical stress in the deformation film to cause generation of electrical power by the deformation film.

Devices and methods for generation and detection of spin waves

The disclosed technology relates generally to magnetic devices, and more particularly to spin torque majority gate devices such as spin torque magnetic devices (STMG), and to methods of fabricating the same. In one aspect, a majority gate device includes a plurality of input zones and an output zone. A magnetic tunneling junction (MTJ) is formed in each of the input zones and the output zone, where the MTJ includes a non-magnetic layer interposed between a free layer stack and a hard layer. The free layer stack in turn includes a bulk perpendicular magnetic anisotropy (PMA) layer on a seed layer, a magnetic layer formed on and in contact with the bulk PMA layer, and a non-magnetic layer formed on the magnetic layer. Each of the bulk PMA layer and the seed layer is configured as a common layer for each of the input zones and the output zone.

Spin torque majority gate device

The disclosed technology generally relates to semiconductor devices and more particularly to selector devices for memory devices having a resistance switching element, particularly resistive random access memory (RRAM) devices. In one aspect, a selector device includes a first barrier structure comprising a first metal and a first semiconductor or a first low bandgap dielectric material, and a second barrier structure comprising a second metal and a second semiconductor or a second low bandgap dielectric material. The selector device additionally includes an insulator interposed between the first semiconductor or the first low bandgap dielectric material and the second semiconductor or the second low bandgap dielectric material. The first barrier structure, the insulator, and the second barrier structure are stacked to form a metal/semiconductor or low bandgap dielectric/insulator/semiconductor or low bandgap dielectric/metal structure.

Selector for RRAM

The present disclosure relates to a method () for depositing a layer on a III-V semiconductor substrate, in which this method comprises providing () a passivated III-V semiconductor substrate comprising a III-V semiconductor surface which has a surface passivation layer provided thereon for preventing oxidation of said III-V semiconductor surface. The surface passivation layer comprises a self-assembled monolayer material obtainable by the reaction on the surface of an organic compound of formula R-A, wherein A is selected from SH, SeH, TeH and SiX. X is selected from H, Cl, O&#x2014;CH, O&#x2014;CH, and O&#x2014;CH, and R is a hydrocarbyl, fluorocarbyl or hydrofluorocarbyl comprising from 5 to 20 carbon atoms. The method further comprises thermally annealing () the III-V semiconductor substrate in a non-oxidizing environment such as to decompose the self-assembled monolayer material, and depositing () a layer on the III-V semiconductor surface in the non-oxidizing environment.

Layer deposition on III-V semiconductors

In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film.

Conformal anti-reflective coating

The present disclosure is related to a dielectric layer comprising a rare-earth aluminate (REAlOwith 0&#x3c;x&#x3c;2) and having a perovskite crystalline structure, wherein the rare-earth aluminate comprises a rare-earth element having an atomic number higher than or equal to 63 and lower than or equal to 71. The disclosure also relates to method of manufacturing of a dielectric stack and a dielectric stack comprising said rare-earth aluminate dielectric layer and further comprising a template stack comprising at least an upper template layer, wherein the upper template layer has a perovskite structure, and wherein the upper template layer is underlying and in contact with the rare-earth aluminate dielectric layer. In a preferred embodiment the dielectric stack further comprises a lower template layer having a crystalline structure, wherein the lower template layer is underlying and in contact with the upper template layer.

Dielectric layer for flash memory device and method for manufacturing thereof

Growing community of inventors

Wilsele, Belgium

Christoph Adelmann