Qorvo US, Inc.

Texas Instruments Corporation

Maxim Integrated Products, Inc.

Christo Pavel Bojkov

Andrew Arthur Ketterson

Robert Charles Dry

Tarak A Railkar

Kevin J Anderson

Deep C Dumka

Michael Roberg

Orlando F Torres

Michael L Krumnow

Dylan Murdock

Ajay Kumar Ghai

Walid M Meliane

Diane Louise Arbuthnot

Duane Wilcoxen

Robert F Kunesh

Terry Hon

Zhi-Qi Li

Matthew Essar

Steve Detlev Cate

Harold Isom

RF devices, and more particularly RF devices with photo-imagable polymers for high frequency enhancements and related methods are disclosed. High frequency enhancements are realized by providing air cavities registered with one or more operating portions of RF devices. The air cavities are formed by photo-imagable polymer structures that provide separation from high dielectric constant materials associated with sealing materials, such as overmold materials, that are typically used for environmental and/or mechanical protection in RF devices. Related methods are disclosed that include forming the photo-imagable polymer structures and corresponding air cavities through various lamination and patterning of photo-imagable polymer layers. Further radiation hardening steps are disclosed that may be applied to the photo-imagable polymer structures after air cavities are formed to promote improved structural integrity of the air cavities during subsequent fabrication steps and during operation of the RF devices.

Radio frequency devices with photo-imageable polymers and related methods

An integrated circuit (IC) package with an embedded heat spreader in a redistribution layer (RDL) is provided. IC packaging facilitates a high density package for ICs, including monolithic microwave integrated circuits (MMICs). However, IC packaging may result in reduced heat removal from an IC, decreasing radio frequency (RF) circuit performance. In an exemplary aspect, an IC package is provided which incorporates an embedded heat spreader within a dielectric layer of an RDL coupled to an IC die. The embedded heat spreader provides efficient heat transfer, robust RF performance, and operation through millimeter wave (mmW) frequencies, all in a miniature low-cost, low-profile surface mountable (SM) package.

Method for packaging an integrated circuit (IC) package with embedded heat spreader in a redistribution layer (RDL)

Semiconductor devices, and more particularly arrangements of fluorinated polymers with low dielectric loss for environmental protection in semiconductor devices are disclosed. Arrangements include conformal coatings or layers of fluorinated polymers that cover a semiconductor die on a package substrate of a semiconductor device. Such fluorinated polymer arrangements may also conformally coat various electrical connections for the semiconductor die, including wire bonds. Fluorinated polymers with low dielectric constants and low moisture permeability may thereby provide reduced moisture ingress in semiconductor devices while also reducing the impact of associated dielectric loss.

Fluorinated polymers with low dielectric loss for environmental protection in semiconductor devices

Monolithic microwave integrated circuits (MMICs) with backside interconnects for fanout-style packaging are disclosed. Fanout-style packaging, such as fanout wafer (FOWLP) or fanout panel-level packaging (FOPLP), facilitates a high density package for MMICs. However, the fanout-style packaging may produce undesired electromagnetic (EM) coupling between a MMIC die and metal features in a redistribution layer (RDL) of the FOW/PLP package and/or a next higher assembly (NHA). In an exemplary aspect, a circuit package according to this disclosure includes the MMIC die and an RDL. The MMIC includes a chip side with components which may undesirably couple to metal signal lines (e.g., package metal interconnects) in the RDL. The chip side of the MMIC is oriented away from the RDL to reduce such EM coupling.

MMICs with backside interconnects for fanout-style packaging

Integrated circuit (IC) package with embedded heat spreader in a redistribution layer (RDL)

Improved structures for spatial power-combining devices are disclosed. A spatial power-combining device includes a plurality of amplifier assemblies and each amplifier assembly includes a body structure that supports an input antenna structure, an amplifier, and an output antenna structure. According to embodiments disclosed herein, the body structure comprises a material that is configured to provide the spatial power-combining device with reduced weight while maintaining good thermal dissipation for heat generated by the amplifiers. In certain embodiments, the body structure may comprise an allotrope of carbon such as graphite or graphene, among others. In certain embodiments, the body structure may include one or more thermal vias configured to dissipate heat from the amplifier.

Structures for spatial power-combining devices

A method includes the steps of fabricating one or more semiconductor devices on a semiconductor wafer and depositing one or more conformal organic environmental protection layers over the semiconductor wafer using a vapor deposition process. By depositing the one or more conformal organic environmental protection layers using a vapor deposition process, thin film conformal organic environmental protection layers may be provided that offer excellent protection against water and oxygen ingress, thus increasing the ruggedness and reliability of the resulting semiconductor die.

Environmental protection for wafer level and package level applications

An integrated circuit including solder balls containing an elastic or resilient material core, a hard or rigid shell substantially enclosing the core, and an electrical contact layer substantially enclosing the shell. The elastic or resilient core serves as a stress buffer layer in a wafer level package (WLP) integrated circuit. The elastic or resilient material core may include an organic plastic material, such as a Divinilbenzene cross-linked co-polymer of relatively high resistance. This material has a relatively good elongation property so that it can effectively absorb forces exerted upon the integrated circuit by, for example, the flexing of a printed circuit board (PCB) or other structure to which the integrated circuit is attached. The hard or rigid shell serves to contain the elastic or resilient core and may include copper. The electrical contact layer serve to provide a good adhesive electrical contact to an under bump metallization (UBM) layer, may include a lead free, Tin-Gold (SnAg) material.

Wafer level package integrated circuit incorporating solder balls containing an organic plastic-core

A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer (preferably silicon nitride) on the chip surface, followed by a polymer layer (, preferably benzocyclobutene) on the first inorganic layer (), and finally an outermost second inorganic layer (, preferably silicon dioxide) on the polymer layer (). A window () in the stack of layers exposes the metallization () of the IC. A patterned seed metal layer (, preferably copper) is on the metallization () in the window and on the second inorganic layer () around the window. A buffer metal layer (, preferably copper) is positioned on the seed metal layer (). A metal reflow element () is attached to the buffer metal ().

Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion

A metal structure () for a bonding pad on integrated circuit wafers, which have interconnecting metallization () protected by an insulating layer () and selectively exposed by windows in the insulating layer. The structure comprises a patterned seed metal layer () positioned on the interconnecting metallization exposed by the window so that the seed metal establishes ohmic contact to the metallization as well as a practically impenetrable seal of the interface between the seed metal and the insulating layer. Further, a metal stud () is formed on the seed metal and aligned with the window. The metal stud is conformally covered by a barrier metal layer () and an outermost bondable metal layer ().

Sealing and protecting integrated circuit bonding pads

A semiconductor device including a contact pad and circuit metallization on the surface of an integrated circuit (IC) chip comprises a stack of protection layers over the surface of the chip. The stack consists of a first inorganic layer (, preferably silicon nitride) on the chip surface, followed by a polymer layer (, preferably benzocyclobutene) on the first inorganic layer (), and finally an outermost second inorganic layer (, preferably silicon dioxide) on the polymer layer (). A window () in the stack of layers exposes the metallization () of the IC. A patterned seed metal layer (, preferably copper) is on the metallization () in the window and on the second inorganic layer () around the window. A buffer metal layer (, preferably copper) is positioned on the seed metal layer (). A metal reflow element () is attached to the buffer metal ().

A method for preparing a bonding pad on an integrated circuit wafer by the steps of depositing a conductive seed layer () on the bonding pad; depositing a metal layer (, and) over a portion of the conductive seed layer; and immersing the wafer in an etchant solution () to remove the portion of the seed layer not covered by the metal layer. The etchant solution contains a chelating agent that bonds ions from the seed layer. When the seed layer is copper or a refractory metal, and the metal layer is gold or palladium, the preferred chelating agent is selected from, but is not limited to, but is not limited to, the families of ethylenediaminetetraacetic acids (EDTA), 8-hydroxy-quinolines, including 8-hydroxy-quinoline-5-sulfonic acid, porphyrins, and phthalocyanines.

Growing community of inventors

Plano, TX, United States of America

Christo Pavel Bojkov