Siemens Aktiengesellschaft

Infineon Technologies Ag

Siemens Aktiengesell Schaft

Future-Shape Gmbh

Christl Lauterbach

Werner Weber

Stefan Jung

Martin Bloch

Georg Braun

Christian Paulus

Frank Schliep

Helmut Albrecht

Udo Ollert

Thomas Sturm

Annelie Sohr

Rupert Glaser

Albrecht Helmut

A processor arrangement having a plurality of processor units and a control computer. Each of the processor units is connected to at least one adjacent processor unit and has one control element and at least one communications interface for providing a data communications link with an adjacent processor unit. The control computer is connected to one of the processor units, and is configured for exchanging information with the processor unit and for assigning one control element of the plurality of control elements to a device that is electrically connected to the processor arrangement for the control of the device.

Processor array arrangement controlled by control computer

Input apparatus including at least one textile fabric carrier, at least one flexible, wire-and/or thread-like electrical conductor comprising at least one weft and/or warp thread of the fabric carrier, and at least one electrically conductive, flexible key device which is electrically connected to a key connection of the conductor, wherein the conductor is designed for the connection of an evaluation device.

Keypad in textiles with capacitive read-out circuit

Contact-making device and method for connecting an electric conductor, in particular a wire-like and/or thread-like electric conductor which is arranged in a textile material, electrically to an electronic component. The device includes a substrate material, and at least one contact, which is formed on the substrate material, to connect the electric conductor electrically to the electronic component, the contact comprising a movable section and an immovable section. The movable section is formed such that, during the electrical connection operation, it is arranged substantially on a surface side opposite the immovable section.

Method for connecting an electric conductor electrically to an electronic component

Method for electrically connecting an electrical conductor to an electronic component including the steps of providing a textile material in which at least one flexible, wire-like and/or thread-like electrical conductor is arranged, providing the electrical conductor relative to an electrically conductive contact point of the electronic component, and electrically connecting the conductor to the contact point comprising the steps of electrically connecting an at least partly electrically conductive auxiliary contact to the conductor, and electrically connecting the auxiliary contact to the contact point, wherein the auxiliary contact is a metal lamina. In one embodiment, the auxiliary contact and the conductor may be joined to one another as they are joined to the contact point.

Construction and electrical connection technique in textile structures

A method for fabricating a microelectronic circuit having an improved electrically conductive element. The method includes providing a finished processed microelectronic circuit having a monolithically integrated coil and having a passivation layer situated above at least the monolithically integrated coil. The method further comprises removing at least part of the passivation layer above the monolithically integrated coil and applying a metal layer above the monolithically integrated coil so that the metal layer is electrically coupled to the monolithically integrated coil.

Method for fabricating a microelectronic circuit including applying metal over and thickening the integrated coil to increase conductivity

A supply voltage is needed in conventional electronic circuits used for processing signals, such as counting pulses. The supply voltage supplies the logic circuit components. Especially apparatuses which have to be operated over a longer period of time or/and in remote sites of use and are dependent upon a supply voltage are impaired with the dependency-related disadvantages, such as the necessity of expensive EEPROMs or significantly increased maintenance expenditure. The present invention relates to an electronic circuit which is provided with an input ( ) for inputting at least one information signal, an energy means ( ) for converting the energy that is present in the at least one information signal into a supply voltage, a control means ( ) for generating at least one switch-on control signal when the information signal is input and a signal processing means ( ) for storing information which is represented by the at least one information signal and/or for evaluating information which is represented by the at least one information signal and for storing the secondary information which is obtained by the evaluation. At least one ferroelectric flipflop ( ) is used. The signal processing means ( ) can be activated by the at least one switch-on control signal for evaluating and/or storing purposes. The at least one information signal can be or is the only energy source for the electronic circuit ( ) during the evaluation and/or storing process.

Electronic circuit for a method for storing information, said circuit comprising ferroelectric flip-flops

A vertically integrated semiconductor component is provided with component levels disposed on different substrates. The substrates are joined by a connecting layer of benzocyclobutene and an electrical connection is provided between component levels by a vertical contact structure. A low-stress gluing is provided by the benzocyclobutene connecting layer.

Vertically integrated semiconductor component

An apparatus for voltage multiplication of the kind required, for example, for programming flash EEPROMs. The apparatus has the advantage that comparatively simple and good regulation of the output voltage can be produced even in integrated circuits in which severe fluctuations in the supply voltage may be allowed.

Apparatus for voltage multiplication with output voltage having low dependence on supply voltage

Vertically integrated semiconductor component and method of producing

A circuit configuration for producing negative voltages includes a first transistor having a first connection connected to an input connection, a second connection connected to an output connection of the circuit configuration and a gate connection connected through a first capacitor to a first clock signal connection. A second transistor has a first connection connected to the gate connection of the first transistor, a second connection connected to the second connection of the first transistor and a gate connection connected to the first connection of the first transistor. A second capacitor has a first connection connected to the second connection of the first transistor and a second connection connected to a second clock signal connection. The transistors are MOS transistors produced in a triple well. A third transistor has a first connection connected to the second connection of the first transistor, a second connection connected to the well(s) containing the transistors and a gate connection connected to the first connection of the first transistor. A charge pump having at least two of the circuit configurations and a method of operating the charge pump are also provided.

Circuit configuration for producing negative voltages, charge pump

A photodiode-FET combination having an optimized layer structure wherein the photodiode and the FET are separated from one another by a separating trench and are separated from the substrate by barrier layers forming a pn-junction in order to avoid tributary currents. A layer sequence is provided formed of an absorption layer grown on in surface-wide fashion, of a photodiode layer that is likewise grown on in surface-wide fashion and which is etched back to the region of light incidence in the region of the photodiode, of a channel layer in the region of the FET, and of a cover layer on the channel layer which forms a gate.

Monolithically integrated photodiode-FET combination

A PIN-FET combination having a basic layer, a first semiconductor layer as an absorption layer or, resepectively, a buffer layer, a second semiconductor layer as a contact layer or, respectively, as a channel layer and a third semiconductor layer as a cover layer grown surface-wide on a substrate. The p.sup.+ -region of the photodiode and, respectively, the gate region of the FET being fashioned therein. The basic layer is undoped or n-doped in the region of the photodiode and is p-doped in the region of the FET and a surface-wide, p-doped layer portion is present in the region of the FET between the channel layer and the substrate.

PIN-FET combination with buried p-layer

A contact structure on indium-containing III-V semiconductor material is comprised of a four layer sequence consisting of an indium layer in direct contact with the semiconductor material, a zinc layer in contact with the indium layer, a chromium-nickel or chromium or palladium or platinum layer in contact with the zinc layer and a gold layer for external contacting with a lead. An exemplary embodiment of such contact structure exhibits specific contact resistance ranging between about 10.sup.-4 and 10.sup.-5 ohm.multidot. cm.sup.2.

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Hohenkirchen-Siegertsbrunn, Germany

Christl Lauterbach