International Business Machines Corporation

Christine Qiqing Ouyang

Alexander Reznicek

Kevin K Chan

Christian Lavoie

Haizhou Yin

Bin Yang

Paul Michael Solomon

Zhen Zhang

Wilfried Haensch

Dae-Gyu Park

Xinhui Wang

Zhibin Ren

Xiaoyan Shao

Thomas Safron Kanarsky

Jinghong Li

Pouya Hashemi

Fei Liu

Pranita Kerber

Jeremy Daniel Schaub

A semiconductor structure includes a first fin structure having a first strain located on a surface of a first insulator layer portion. The first fin structure includes a first doped silicon germanium alloy fin portion having a first germanium content and a silicon germanium alloy fin portion having a third germanium content. A second fin structure having a second strain is located on a surface of a second insulator layer portion. The second fin structure includes a second doped silicon germanium alloy fin portion having a second germanium content and a silicon germanium alloy fin portion having the third germanium content, wherein the first germanium content differs from the second germanium content and the third germanium content is greater than the first and second germanium contents, and wherein the first strain differs from the second strain.

Structure and method for multi-threshold voltage adjusted silicon germanium alloy devices with same silicon germanium content

A method for monolithically integrating semiconductor waveguides, photodetectors and logic devices, i.e., field effect transistors, on a same substrate is provided. The method includes the use of a double semiconductor-on-insulator substrate that includes from bottom to top, a handle substrate, a first insulator layer, a first semiconductor material layer, a second insulator layer, and a second semiconductor material layer. The waveguides, photodetectors and logic devices can be formed in different regions of the substrate and are present atop a first insulator layer of the double semiconductor-on-insulator substrate.

Structure and method of integrating waveguides, photodetectors and logic devices

A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

Multigate structure formed with electroless metal deposition

A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.

finFETs and methods of making same

finFETS and methods of making same

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Yorktown Heights, NY, United States of America

Christine Qiqing Ouyang